Method of fabricating capacitor

Details Method of fabricating capacitor Method of fabricating capacitor

1999-12-20

2001-02-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S255000, C438S256000, C438S396000

Reexamination Certificate

active

06190962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for an integrated circuit (IC). More particularly, the present invention relates to a method for fabricating a dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
Dynamic random access memory (DRAM) is a circuit structure that increases the integrated circuit (IC) density, and is widely used for storing information in the electrical industry. The mode of storing information or data is determined by the charged state of a capacitor in a memory cell, while the information is accessed by the memory cell and a read/program circuit peripheral to the wafer.
The memory cell developed at present is made of a transfer field effect transistor (TFET) and a storage capacitor.
FIG. 1
is a circuit diagram illustrating memory elements of a DRAM device. From the diagram, it can be seen that a capacitor (C) is screened from the arrays of capacitors on the surface of the semiconductor substrate, which capacitor stores the data by using its discharging characteristics. This is commonly achieved by storing binary bit data into all capacitors, where each capacitor shows a logic zero when it is uncharged, and a logic one when it is charged.
Usually, there is a dielectric layer
102
between an upper electrode
101
and a lower electrode
100
of the capacitor (C) to provide a required dielectric constant between the electrodes. The capacitor is in turn coupled to a bit line (BL), wherein the capacitor is discharged to perform a read/program function. The charging/discharging state of the capacitor is switched by the TFET. This method comprises connecting the bit line (BL) to the source of the TFET, connecting the capacitor (C) to the drain of the TFET, and sending a signal in the word line (WL) to the gate of the TEFT. Accordingly, the method determines whether the capacitor (C) is connected to the bit line (BL).
As the number of transistors on the conventional DRAM wafer increases with a gradual decrease in the transistor size, it becomes difficult to maintain the capacitor within an acceptable range of signal-to-noise ratio level when it is storing charges. On the other hand, if the capacitor storage capacity is decreased to reduce the noise, the refresh cycles of the signal storage charges are necessarily increased.
As the area occupied by the capacitor is limited by the size of the memory cell, it is necessary to develop a more effective capacitor, which provides a large capacitance as desired, while not increasing the horizontal space occupied on the substrate. As a result, the rule of the semiconductor process is satisfied. The most common capacitor structures generally include a trench capacitor, a cylinder capacitor, and a stacked capacitor. Among these capacitors, the trench capacitor is seldom considered because it is difficult to make. The cylinder capacitor and the stacked capacitor are structures that extend vertically upwards from the substrate, so that the surface area of the capacitor is largely increased and the capacitors have different design structures. However, numerous repetitive steps involved in manufacturing the cylinder capacitor or the stacked capacitor increase the process complexity and the manufacturing cost.
FIGS. 2A through 2D
illustrate steps for fabricating conventional DRAM cylinder capacitor.
Referring to
FIG. 2A
, a semiconductor substrate
200
is provided with a dielectric layer
202
formed thereon. A photolithography and etching process is performed to form a contact opening
204
in the dielectric layer
202
, so that a part of the semiconductor substrate
200
is exposed.
Referring to
FIG. 2B
, a conducting layer
206
, which is made of amorphous silicon, is formed on the dielectric layer
202
to fill the contact opening
204
. A photolithography and etching process is further performed to remove a part of the conducting layer
206
, so that a lower electrode
208
which connects to the semiconductor substrate
200
is formed on the dielectric layer
202
, as shown in FIG.
2
C.
Referring to
FIG. 2D
, a hemispherical grain (HSG) layer is coated on the lower electrode
208
, so that a HSG lower electrode
210
with an increased surface area is formed.
Generally, it takes a long time to deposit an amorphous silicon layer. Therefore, as it is necessary to increase the thickness of the amorphous silicon layer in order to meet the demand for increased capacitance, the time for depositing the amorphous layer inevitably becomes longer. Furthermore, the manufacture of a lower electrode of the capacitor includes etching the amorphous silicon layer, which not only involves etching the silicon layer in the memory cell, but also removing the silicon layer in the peripheral region. As a result, a height difference between the cell memory and the peripheral region makes up a thickness sum of a lower electrode, a dielectric film, and an upper electrode. With an increased thickness of the silicon layer being deposited, the height difference between the cell memory and the peripheral region for manufacturing the capacitor increases. Therefore, a dielectric layer is usually deposited after the manufacture of the capacitor, followed by performing chemical mechanical polishing (CMP) to achieve a global planarization.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a capacitor, which method provides a semiconductor substrate with a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back. The second silicon nitride layer and the second dielectric layer are removed to expose a part of the conducting layer. A hemispherical grain (HSG) layer is coated on the exposed part of the conducting layer to complete manufacture of a lower electrode, while the lower electrode is covered by a dielectric film and an upper electrode to complete manufacture of the capacitor.
As embodied and broadly described herein, the invention provides a fabrication method for a capacitor, by which a thickness of the conducting layer is approximately equal to a radius of the terminal contact opening, so that the capacitance is controlled through adjusting the thickness of the second dielectric layer. Therefore, the thickness of the conducting layer is not directly related to the capacitance, regardless of the amount of the capacitance. So, the time required for depositing the conducting layer remains unchanged.
According to the present invention, only the second dielectric layer above the capacitor region is removed to expose the lower electrode when the lower electrode is manufactured. After the manufacture of the capacitor, the height difference between the peripheral region and the capacitor region merely constitutes the thicknesses of the dielectric film and the upper electrode, wherein the height difference is much smaller than that of the conventional capacitor. Thus, a planarization step, which involves CMP, can be skipped to simplify the whole process. In addition, terminal contact opening is formed in a self-aligned manner, so a patterning step using a mask would be redundant in the process. Therefore, the overall process is simplified with reduced process complexity.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are

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