Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-13
2001-02-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S243000, C438S244000, C438S246000, C438S247000, C438S248000, C438S386000, C438S387000, C438S389000, C438S390000, C438S391000
Reexamination Certificate
active
06190971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to transistors having straps connecting transistor devices to storage devices.
2. Description of the Related Art
Vertical transistors are known in the art of semiconductor manufacturing for reducing the overall size of the transistor device and, therefore, for allowing an increase in the scaling of such devices. However, conventional vertical transistors have substantial problems associated with the formation of the strap (e.g., the conductive connection between the storage device and the gate/drain of the transistor).
The invention overcomes these problems by forming a self-aligned buried strap within a partially vertical transistor, as specified below.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for manufacturing an integrated circuit device including forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and the step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in the substrate adjacent the gate conductor and forming a contact over the diffusion region and isolated from the gate conductor, wherein a voltage in the gate conductor forms a conductive region in the substrate adjacent the step and the conductive region electrically connects the strap and the contact.
Further, the forming of the isolation opening in the substrate and the filling of the isolation opening with an isolation material includes forming a first portion of an active area isolation region. The method also includes forming active area stripes to form a second portion of the active area isolation region.
The forming of the storage device includes forming a deep trench capacitor and the strap bisects a plane of the deep trench capacitor. Further, the gate opening is wider than the strap opening and the strap opening is wider than the isolation opening. The integrated circuit device is a partially vertical transistor and the strap also is a source region and the contact is a drain region.
The invention also comprises a method of manufacturing an integrated circuit chip that includes forming an opening having at least one step in a substrate, forming a first conductor in the opening below the step, forming a first diffusion region in the substrate adjacent the first conductor, forming a gate conductor over the step, forming a second conductor over the substrate adjacent the gate conductor and forming a second diffusion region in the substrate adjacent the second conductor. The forming of the opening further includes lithographically forming a gate opening in the substrate, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening and forming an isolation opening in the substrate using the second spacers to align the isolation opening. The isolation opening is filled with an isolation material and the forming of the isolation opening in the substrate and the filling of the isolation opening with an isolation material includes forming a first portion of an active area isolation region, the method further includes forming active area stripes to form a second portion of the active area isolation region. The first spacers and a portion of the second spacers are removed to form the step in the opening and the second spacers are the first conductor. Further, the gate opening is wider than the strap opening and the strap opening is wider than the isolation opening. A voltage in the gate conductor forms a conductive region in the substrate adjacent the step and the conductive region electrically connects the first conductor and the second conductor. The opening is formed over a deep trench capacitor and the first conductor bisects a plane of the deep trench capacitor. The integrated circuit device is a partially vertical transistor and the first conductor is a source region and the second conductor is a drain region.
An integrated circuit chip according to the invention includes a substrate, an opening in the substrate, the opening having at least one step, a first conductor in the opening below the step, a first diffusion region in the substrate adjacent the first conductor, a gate conductor over the step, a second conductor over the substrate adjacent the gate conductor and a second diffusion region in the substrate adjacent the second conductor.
The integrated circuit chip opening includes a lithographically formed gate opening, a strap opening aligned with the gate opening using first spacers and an isolation opening aligned with the strap opening using second spacers. The integrated circuit chip also includes an isolation material filling the isolation opening and the isolation material includes a first portion of an active area isolation region and the integrated circuit chip further includes active area stripes forming a second portion of the active area isolation region.
The first spacers and a portion of the second spacers are removed to form the step in the opening and the second spacers include the first conductor. The gate opening is wider than the strap opening and the strap opening is wider than the isolation opening. A voltage in the gate conductor forms a conductive region in the substrate adjacent the step and the conductive region electrically connects the first conductor and the second conductor. The opening is formed over a deep trench capacitor and the first conductor bisects a plane of the deep trench capacitor. The first conductor includes a source region and the second conductor includes a drain region and the integrated circuit chip includes a partially vertical transistor.
By reducing the amount of lithographic processing, the invention avoids problems commonly associated with lithographic processes, including size reduction problems and alignment inaccuracies. Further, with the invention by forming the step in such a self-aligned manner, the spacing between the diffusion regions and the vertical transistor portion is very precise. This allows the device to be made smaller (which makes the device less expensive and faster), reduces the number of defects which results in an overall superior product when compared to conventional structures.
In addition, the invention forms the straps to bisect a plane of the storage devices which allows a more reliable connections between the storage device and the strap.
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Gruening Ulrike
Radens Carl J.
International Business Machines - Corporation
Kennedy Jennifer M.
McGinn & Gibb PLLC
Niebling John F.
Petraske, Esq. Eric W.
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