Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-16
2001-11-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06321370
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for processing the layout of logic elements of semiconductor integrated circuits, and particularly to a method for processing the layout of logic elements of semiconductor integrated circuits in which the layout of logic elements or logic element groups are instructed from outside, and the layout of logic elements is optimized with respect to signal transfer delays.
BACKGROUND ART
Examples of the prior art related to a method for processing the layout of logic elements of semiconductor integrated circuits include a technique described in the Japanese Patent Laid-Open Publication No. 8-274177 is known. This example of the prior art provides a method for processing the layout of logic elements to optimize the layout of the logic elements with respect to signal transfer delays in which each logic element of a logic element group, which is logically divided into logic block units, each consisting of logic elements, and logically designed in a hierarchical structure, and is laid out on a semiconductor integrated circuit board, with the logic elements belonging to the same logic block being clustered together in the layout.
According to the example of the prior art described in the aforementioned Japanese Patent Laid-Open Publication No. 7-73643, layout is processed by causing information for optimizing the layout of logic elements with respect to signal transfer delays to be automatically recognized by the connection relationship among the logic elements.
However, this example of the prior art takes into consideration the connection relationship among all the logic elements and, since semiconductor integrated circuits have recently taken on much larger scales, it is anticipated that enormous processing hours will be required if the entire layout is to be processed in this manner, which might prove to be a factor to prevent the layout to be designed in a short period of time.
Yet, since logic elements to be taken account of in addressing signal delays or the like are limited to some specific logic elements, and likewise what governs the operating speed of a semiconductor integrated circuit is the signal transfer time pertaining to connection among specific logic elements, it was found unnecessary to optimize the layout of all the logic elements.
An object of the present invention, therefore, is to provide a method for processing the layout of logic elements of semiconductor integrated circuits capable of enabling the layout design to be accomplished in a short period of time by optimizing the layout of logic elements.
DISCLOSURE OF THE INVENTION
To accomplish the above-mentioned object, the present invention provides for the following configuration.
1. The optimal layout of logic blocks is determined by providing in advance a logic block file consisting at least of logic block names, logic block sizes, and information on connection relationships with other logic blocks; displaying a list of logic block names extracted from the logic block file as a logic block name list; laying out logic blocks chosen at random from the logic block name list on the aforesaid circuit board layout drawing in accordance with logic block sizes in the aforementioned logic block file; and displaying the relationships among the laid-out logic blocks according to the connection relationships with other logic blocks in the aforementioned logic block file. This enables the operator to readily confirm whether or not the layout of logic blocks satisfies the conditions of locatability on a display screen, and it is highly effective in determining the layout of semiconductor integrated circuits.
2. A table showing the matching between connection relationships among logic blocks and the conditions of locatability pertaining to the relative positions of logic blocks is provided in advance, and any logic block failing to satisfy the conditions of locatability is made readily recognizable by the operator by identifying the logic block. This enables the operator to readily know whether or not the position in which each logic block has been laid out is appropriate.
3. As regards any logic block failing to satisfy the conditions of locatability, the logic block can be laid out in a position satisfying the conditions of locatability by identifying and shifting the logic block.
REFERENCES:
patent: 5666288 (1997-09-01), Jones et al.
patent: 06-124320 (1994-05-01), None
patent: 10011489A (1998-01-01), None
Hiyama Toru
Suzuki Katsuyoshi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Smith Matthew
Speight Jibreel
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