Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-21
2001-11-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S301000, C438S303000
Reexamination Certificate
active
06323095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor processing, and, more particularly, to a method for reducing junction capacitance using a halo implant photomask.
2. Description of the Related Art
Semiconductor devices, such as transistors, are formed through a series of steps. First a gate is formed over a portion of a substrate. Implants are then conducted to form source/drain (S/D) regions of the transistor. In an N type transistor, N type dopants are implanted in a P type substrate. In a P type transistor, an N type well is typically formed in a portion of the substrate, and the gate is formed over a portion of the N type well. P type dopants are then implanted to form the S/D regions.
Typically, several implantation steps are used to form the transistor. In the following discussion, fabrication of an N type transistor is described. First, a lightly doped drain (LDD) implant is performed using an N type dopant, such as Arsenic. Next, a halo implant is performed using a P type dopant, such as Boron. The halo implant is used to reduce short channel effects associated with the transistor. Short channel effects cause the threshold voltage of the transistor to decrease as the geometry shrinks. Typically, at least a portion of the halo implant is performed at an angle so that some of the dopant is implanted beneath the gate. Following the halo implant, spacers are formed on the gate, and a S/D implant is performed with an N type dopant, such as Phosphorous.
One disadvantage of using a halo implant to reduce the short channel effects is that the presence of the P type halo dopant in the N type S/D regions increases the junction capacitance of the transistor. Increased junction capacitance results in a less efficient transistor.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for forming a semiconductor device. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance.
Another aspect of the present invention is seen in a semiconductor device including a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.
REFERENCES:
patent: 5504023 (1996-04-01), Hong
patent: 5963811 (1999-10-01), Chern
patent: 5976937 (1999-11-01), Rodder et al.
patent: 0535917A2 (1993-04-01), None
patent: 0535917A3 (1996-06-01), None
International Search Report for International Application Serial No. PCT/US00/24422 Filed Sep. 6, 2000.
Cheek Jon D.
Dawson Robert
Michael Mark W.
Advanced Micro Devices , Inc.
Elms Richard
Owens Beth E.
Williams Morgan & Amerson P.C.
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