Pattern forming method

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Electron beam imaging

Reexamination Certificate

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C430S030000

Reexamination Certificate

active

06316163

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a pattern forming method for forming fine patterns with high accuracy and throughput. More particularly, the present invention relates to a method for generating pattern data for light exposure and charged particle beam exposure from device design patterns in order to transfer patterns on the same photosensitive material using light exposure and charged particle beam exposure.
Photolithography in semiconductor manufacturing steps is widely used for the production of devices thanking to its advantages such as simplicity of processing and low cost. Recently, elements as fine as 0.25 &mgr;m or less have been realized as a result of the introduction of short wavelength utilizing KrF excimer laser light sources. In order to improve fineness further, efforts are being put on the development of ArF excimer laser light sources having shorter wavelengths and Revenson type phase shift masks which are regarded promising as mass production lithographic tools compatible with 0.15 &mgr;m rules. However, there are many disadvantages to be solved to realize them, which has increased the time required for the development of the same and behind the rate at which devices are made finer and it is being worried about being impossible to catch up a fineness speed of the device.
On the contrary, electron beam lithography which is the most promising candidate as the post-photolithography technique (in the following description, “electron beam lithography” obviously implies charged particle lithography) has proved itself capable of processing on the order of 0.01 &mgr;m using narrowed beams. Although this technique has no pressing disadvantage from the viewpoint of improving fineness, it has a disadvantage with throughput when viewed as a tool for the mass production of devices. Specifically, this technique inevitably takes time because it sequentially draws fine patterns one by one. In order to reduce such drawing time, several apparatuses have been developed which employ methods such as exposure method of character projection wherein repetitive parts of an ULSI pattern are simultaneously drawn partially. However, the use of such apparatuses has been still unsuccessful in catching up the through put of photolithography.
As a method of increasing the throughput of electron beam lithography, proposals have been made on the so-called mixing and matching of light and electron beams in the same layer. This method is to perform pattern transfer on to the same resist using light exposure and electron beam exposure to reduce areas subjected to electron beam exposure, thereby increasing the number of wafers which can be processed by an electron beam lithography apparatus per hour. For example, Jpn. Pat. Appln. KOKAI Publication No. 4-155812 discloses the use of light exposure and electron beam exposure employing a phase shift mask in transferring patterns on to the same resist during a lithographic step for pattern formation. According to the publication, most of patterns to form an element are transferred using the phase shift mask and areas having disadvantages attributable to the position of the phase shifter are corrected by means of electron beam lithography, thereby reducing areas to be subjected to electron beam lithography as much as possible to increase the number of wafers which can be processed by the electron beam lithography apparatus per hour.
Although this method reduces areas to be drawn using electron beams, it can not be adapted to finer devices in future because it is not capable of pattern transfer at resolutions below the limit of the resolution of the phase shift mask. Especially, ultra-resolution techniques such as the Revenson type phase shift mask may be limited to patterns having regular lines and spaces of memory LSIs and can not be adapted to increased fineness of random patterns which are characteristic of logic devices.
Further, since LSIs are manufactured through many repetitive lithographic steps, they have variations in processing at those steps and errors in alignment of layers. It is impossible to eliminate those factors completely, although various measures are being taken to suppress them as much as possible. This disadvantage is encountered also in performing pattern transfer on to the same resist using light exposure and electron beam exposure. According to the above-described method, pattern sizes become too large or small or gaps are formed at areas where patterns formed by light exposure and electron beam exposure are connected because such variations in processing and alignment errors are not taken into account in this method.
The variable beam shaping method capable of providing a variety of beam shapes is used to form irregular patterns as seen on, for example, logic circuits using electron beam exposure. The variable beam shaping method controls an optical overlap between a first shaping aperture and a second shaping aperture using a shaping deflector, so that the shapes and sizes of electron beams can be varied with flexibility.
However, a disadvantage arises in that the accuracy of beam sizes is directly affected by the deflecting accuracy of the shaping deflector. Further, insulation materials are gradually deposited on the surface of structures between the first and second shaping apertures and are charged to cause a change in an electrostatic field in the path of electron beams, which results in a shift of the position of an image of the first aperture projected upon the second shaping aperture from a desired position. Since the amount of the deposited insulation materials and the charge thereof change over time, beam sizes also change over time. Therefore, even if the beam sizes are calibrated before lithography, patterns formed at the beginning and the end of lithography are in different sizes because the accuracy of beam sizes gradually changes during lithography.
The disadvantage of overlapping deviations will now be described with reference to
FIGS. 1A through 1D
. If a design pattern is divided into a light-exposed pattern A and an electron-beam-exposed pattern B simply based on the sizes thereof, since the light-exposed pattern A and electron-beam-exposed pattern B are contact to each other (FIG.
1
A), an error in the overlapping of the light exposure and electron beam exposure as described above results in a gap in the area which must be contact (
FIG. 1B
) to disable normal operation of the element.
An article titled “Electron beam/DUV intra-level mix-and-match lithography for random logic 0.25 &mgr;m CMOS” (R. Jonckheere et al., Microelectronic Engineering 27 (1995) pp. 231-234) discloses mix-and-match in the same layer wherein pattern transfers on the same resist are performed using light exposure utilizing a deep-UV stepper and electron beam exposure utilizing a Gausian electron beam lithography apparatus at a lithographic step for pattern formation. According to this article, patterns are divided using 0.4 &mgr;m as a reference, and patterns of 0.4 &mgr;m or more are exposed by deep-UV light whereas patterns less than 0.4 &mgr;m are drawn directly on a wafer using electron beams. In order to absorb errors in overlapping the light exposure and electron beam exposure, the light-exposed patterns and electron-beam-exposed patterns are exposed such that they overlap by 0.1 &mgr;m (FIG.
1
C). By overlapping the patterns in such a manner, it is possible to prevent discontinuation of patterns in areas where they are to be contact even if there is overlapping deviations (FIG.
1
D).
The above-cited article discloses two methods for generating such overlapping patterns. The first method is to move the outline line of a light-exposed pattern outward of the pattern to increase the sizes of the pattern, thereby overlapping it with an electron-beam-exposed pattern (such a processing is referred to as “sizing processing” or “resize processing”). The second method is to move the outline line of an electron-beam-exposed pattern outward of the pattern to increase the sizes of the pattern, thereby ove

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