Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-20
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S398000, C438S713000, C438S673000, C438S701000, C438S665000, C438S964000
Reexamination Certificate
active
06303435
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89103946, filed Mar. 6, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor memory capacitor. More particularly, the present invention relates to a method of fabricating a wide-based box-structured capacitor containing hemi-spherical grains.
2. Description of Related Art
When semiconductor manufacture moves into the deep sub-micron process, the device size becomes smaller and the available space for capacitors decreases. In contrast, as the application software increases in size, the required storage capacity of the capacitor needs to be larger. Consequently, the method for fabricating the capacitor in a dynamic random access memory (DRAM) device has to be changed, in order to be compatible with the market requirement for smaller device size and larger memory size.
The capacitor is the heart for storing information in the DRAM device. As long as the capacitor stores more charges, less damaging influences are induced by noise, for example, soft errors, which are caused by &agr; particles, can be greatly reduced during information reading; furthermore, the frequency for refresh can be reduced as well.
The storage capacity of the conventional DRAM device is small because a two-dimensional capacitor, that is, a planar type capacitor, is used in the integrated circuit manufacture process. The planar type capacitor takes quite large areas of a semiconductor substrate to store charges; therefore, it is not suitable for the design of high-integration devices. Three-dimensional capacitors are used for high-integration DRAM devices.
However, simple structures of three-dimensional capacitors nowadays can no longer satisfy the need for the memory device of higher integration. Therefore, methods for increasing surface areas of DRAM capacitors within small available spaces for capacitors have been developed. Variant structures have been used for capacitors to increase the storage capacity of the memory device, such as stacked types and trench types. Stacked type structures includes double-stacked type, fin-structured type, cylindrical type, spread-stacked type and box-structured type structures.
It is an important task for capacitors to maintain enough storage capacity in processes of semiconductor manufacture below 0.25 &mgr;m. One way of increasing the storage capacity for capacitors is to increase the surface areas of capacitors. Taking crown-structured capacitors for example, hemi-spherical grains (HSG) are formed on the surfaces of lower electrodes of the crown-structured capacitors to increase the storage capacity of capacitors in processes of semiconductor manufacture below 0.18 &mgr;m.
FIG. 1A
to
FIG. 1C
are schematic, cross-sectional views illustrating the process steps of fabricating a lower electrode of a box-structured DRAM capacitor according to the prior art. Referring to
FIG. 1A
, source/drains
102
are formed in a substrate
100
. A silicon oxide layer
104
is deposited on substrate
100
, and then node contact openings
106
are formed by photolithography and etching. A doped amorphous silicon layer
110
is deposited on substrate
100
and inside openings
106
by low-pressure chemical vapor deposition (LPCVD) at about 530 degrees Centigrade.
Referring to
FIG. 1B
, amorphous silicon layer
110
is defined to form lower electrodes
110
a.
Referring to
FIG. 1C
, hemi-spherical silicon grains (HSG-Si)
112
are grown on the surfaces of lower electrodes
110
a,
and lower electrodes
110
b
with larger surface areas are formed thereon. Because of the requirement for high integration, the areas for forming capacitors are limited. Within these available areas, if a distance
114
between two adjacent electrodes is too short, hemi-spherical silicon grains
112
on the surfaces of adjacent electrodes
110
b
contact each other and induce short circuits. On the contrary, if distance
114
is too long, then lower electrodes
110
b
fall down due to overly thin bases.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a wide-based box-structured capacitor containing hemi-spherical grains, so that the lower electrodes are not so thin that they fall down. Furthermore, it increases integration for capacitors but cause no more short circuits problems.
As embodied and broadly described herein, a substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening that exposes the source/drain. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. A first etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer until the first dielectric layer is exposed and a lower electrode is formed thereon in the node contact opening and on the surrounding first dielectric layer. The first etching step comprises the usage of a first flow speed for chlorine and a second flow speed for hydrogen bromide. A second etching step is performed on the lower electrode with a third flow speed of chlorine and a fourth flow speed of hydrogen bromide. The first flow speed is higher than the third flow speed and the second flow speed is lower than the fourth flow speed. A wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide and duration of the second etching step. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.
As embodied and broadly described herein, hemi-spherical silicon grains only can grow on the surface of the doped amorphous silicon layer, but not on the surface of the doped polysilicon layer that is formed before the formation of the doped amorphous silicon layer. Therefore, the growth of hemi-spherical silicon grains does not cause bridging between adjacent lower electrodes, nor induce short circuits in the capacitors. Moreover, the bases of the lower electrodes are wider than the tops of the lower electrodes, so that the lower electrodes do not easily fall down.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5316616 (1994-05-01), Nakamura et al.
patent: 5515984 (1996-05-01), Yokayama et al.
patent: 5707487 (1998-01-01), Hori et al.
patent: 5792691 (1998-08-01), Koga
patent: 5858837 (1999-01-01), Sakoh et al.
patent: 6013549 (2000-01-01), Han et al.
patent: 6124161 (2000-09-01), Chern et al.
patent: 6177326 (2001-01-01), Wu et al.
patent: 6204191 (2001-03-01), Jung et al.
Huang Jiawei
J.C. Patents
Kennedy Jennifer M.
Niebling John F.
United Microelectronics Corp.
LandOfFree
Method of fabricating a wide-based box-structured capacitor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a wide-based box-structured capacitor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a wide-based box-structured capacitor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2605395