Method for manufacturing a split game type transistor

Details Method for manufacturing a split game type transistor Method for manufacturing a split game type transistor

1999-02-25

2001-02-06

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S594000

Reexamination Certificate

active

06184088

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a split gate type transistor and a method for manufacturing the same. Particularly, the present invention relates to a split gate type transistor employable as memory cells in non-volatile semiconductor memory devices and also to a method for manufacturing the same.
2. Description of the Related Art
Recently, non-volatile semiconductor memory devices such as ferro-electric Random Access Memory, Erasable and Programmable Read Only Memory (EPROM) and EEPROM have become increasingly popular. EPROMs and EEPROMs have a plurality of memory cells having floating gates and control gates. EEPROMs include flash EEPROMs which can perform data erasure for all of the memory cells or partial data erasure for each of a plurality of block memory cells. Split gate type cells and stacked gate type cells are present in the memory cells of the flash EEPROM.
In the flash EEPROM, the stacked gate type memory cell has no selector transistor, and thus it cannot make an ON-OFF selection by itself. Accordingly, when excess charges are extracted from the floating gate electrode in performing data erasure, a problem of excess erasure arises. For example, even if 0V is applied to control gate electrodes so as to deenergize the memory cells, those memory cells which were subject to excess erasure are energized. Consequently, electric current constantly flows into the memory cells making it impossibe to read data stored in the memory cells. In order to prevent such excess erasure from occurring, the erasing procedures in the memory device are preferably controlled precisely by a peripheral circuit or an external circuit.
Split gate type memory cells include a selector transistor which obviates the problem of excess erasure. International Patent Publication WO92/18980 discloses a flash EEPROM employing split gate type memory cells.
FIG. 1
is a schematic cross-sectional view of an example of a prior art split gate type memory cell
1
. The split gate type memory cell (split gate type transistor)
1
has an N-type conductive source area
3
and an N-type conductive drain area
4
which are defined on a P-type conductive single crystal silicon substrate
2
, a floating gate
7
disposed on a gate insulating film
6
on a channel
5
present between the source area
3
and the drain area
4
, and a control gate electrode
9
disposed on an insulating film
19
and a tunnel insulating film
8
on the floating gate electrode
7
. The arrow B in
FIG. 1
shows movement of electrons from the floating gate
7
to the control gate electrode
9
in the erasure mode; while the arrow C shows movement of electrons from the channel area
5
to the floating gate electrode
7
in the write mode.
The insulating film
19
is formed with a Local Oxidation on Silicon (LOCOS) process. The floating gate
7
has lips
7
b
formed to extend upward from the upper edges thereof. The control gate electrode
9
has a first part serving as a selector gate
10
disposed on the channel
5
and the insulating films
6
and
8
and a second part disposed on the floating gate electrode
7
and the insulating films
6
and
8
. The selector gate
10
, the source area
3
and the drain area
4
comprise a selector transistor
11
. Accordingly, the split gate type memory cell
1
has the transistor consisting of the floating gate electrode
7
, the control gate electrode
9
, the source area
3
and the drain area
4
, connected in series with the selector transistor
11
.
FIG. 2A
is a schematic cross-sectional view showing a part of a memory cell array having a plurality of the split gate type memory cells
1
, as disclosed in WO92/18980. The memory cells
1
are arranged in the form of a matrix on the silicon substrate
2
.
FIG. 2B
is a schematic plan view showing a part of the memory cell array.
FIG. 2A
is a cross section taken along the line
2
A—
2
A in FIG.
2
B.
Each pair of adjacent memory cells
1
a
and
1
b
share the source area
3
. The floating gate electrode
7
and the control gate electrode
9
of one memory cell
1
a
and those of the other memory cell
1
b
are arranged symmetrically on each side of the source area
3
. Such symmetrical arrangement reduces the area to be occupied by the memory cells on the substrate
2
. As shown in
FIG. 2B
, a field insulating film
13
for separating the memory cells
1
from one another is formed on the substrate
2
. Each pair of memory cells
1
a,
1
b
arranged in column also share the control gate electrode
9
, with each control gate
9
forming a word line. The drain areas
4
in the pairs of memory cells
1
a,
1
b
arranged in row are connected to a common bit line (not shown) via line contacts
14
, respectively.
FIG. 3A
is a schematic cross-sectional view showing a part of memory cell array having a plurality of split gate type memory cells disclosed in U.S. Pat. No. 5,029,130. Compared with
FIG. 2A
, the arrangement of the memory cells, the drain area
4
and the source area
3
are replaced with each other.
FIG. 3B
is a schematic plan view showing a part of the memory cell array.
A method for manufacturing a memory cell array
150
is described with reference to
FIGS. 4A
to
4
G.
Step 1 (FIG.
4
A): The silicon oxide gate insulating film
6
is formed on a device forming area of the substrate
2
according to the thermal oxidation method, and then a doped polysilicon film
31
is formed on the gate insulating film
6
. A silicon nitride film
32
is formed over the entire surface of the doped polysilicon film
31
employing the Low Pressure Chemical Vapor Deposition (LPCVD) method. After a resist is applied over the entire surface of the silicon nitride film
32
, the resist is partially removed by known photolithographic procedures to form an etching mask
33
for forming the floating gate
7
.
Step 2 (FIG.
4
B): After the silicon nitride film
32
is etched by means of anisotropic etching employing the etching mask
33
, the etching mask
33
is removed. Next, the doped polysilicon film
31
is partly oxidized by means of LOCOS employing the partially etched silicon nitride film
32
as a mask to form the insulating film
19
. In this process, the insulating film
19
intrudes into the edge portions of the silicon nitride film
32
to form bird's beaks
19
a.
Step 3 (FIG.
4
C): After the silicon nitride film
32
is removed, the doped polysilicon film
31
is etched by means of anisotropic etching employing the insulating film
19
as an etching mask. Thus, the doped polysilicon film
31
remaining after etching constitutes the floating gate electrodes
7
. In this process, since the insulating film
19
has bird's beaks
19
a
formed thereon, the sharp lips
7
b
are formed along the upper edges of the floating gate
7
below the bird's beaks
19
a.
Step 4 (FIG.
4
D): The silicon oxide tunnel insulating film
8
is formed by thermal oxidation, LPCVD or a combination thereof over the entire surface of the device formed in Step 3.
Step 5 (FIG.
4
E): A doped polysilicon film
34
is formed over the entire surface of the device formed in Step 4.
Step 6 (FIG.
4
F): After a resist is applied over the entire surface of the device formed by in Step 5, an etching mask
35
is formed by means of photolithography.
Step 7 (FIG.
4
G): The doped polysilicon film
34
is etched by anisotropic etching employing the etching mask
35
to form the control gate electrodes
9
. Then, the etching mask
35
is removed.
As shown in
FIG. 5
, at the initial stage of forming the tunnel insulating film
8
in Step 4, an incomplete silicon oxide film
8
a
attributed to native oxide film, structural transition layer, etc. is formed. This incomplete silicon oxide film
8
a
contains not only silicon oxide having the complete O—Si—O bond but also dangling bonds not having the O—Si—O bond. While the process proceeds from Step 3 to Step 4, since lateral faces of the floating gate electrode
7
are exposed to the outside air, a native oxide film is formed on the surface of the

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