Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-18
2001-11-06
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000
Reexamination Certificate
active
06312996
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device and a method for fabricating the same, and more particularly relates to a power MOSFET with a reduced ON-state resistance but with an increased drain-source breakdown voltage and to a method for fabricating the same.
First, a conventional semiconductor device with a structure for increasing a drain-source breakdown voltage will be described with reference to FIG.
10
. This semiconductor device is described in Japanese Laid-Open Publication No. 4-107877, which was filed by Matsushita Electronics Corporation.
This device includes: an n-type source region
107
and an n-type extended drain region
103
, which are both formed within a p-type silicon substrate
104
; and a p-type buried region
102
enclosed in the n-type extended drain region
103
. In part of the n-type extended drain region
103
, a drain contact region
114
is provided to be in electrical contact with a drain electrode
110
. The n-type source region
107
, as well as a substrate contact region
108
formed within the surface of the p-type silicon substrate
104
, is in electrical contact with a source electrode
111
. And an anti-punchthrough region
109
is provided to surround the source region
107
and the substrate contact region
108
.
A region between the source region
107
and the extended drain region
103
functions as a channel region. A gate electrode
106
is provided over the surface of the p-type silicon substrate
104
with a gate insulating film interposed therebetween. And the surface of the p-type silicon substrate
104
is covered with a thermal oxide film
105
.
This semiconductor device is characterized by including: the n-type extended drain region
103
, which is formed by a diffusion process within the p-type silicon substrate
104
to have a relatively low dopant concentration; and the p-type buried region
102
formed inside the n-type extended drain region
103
.
FIG. 11
illustrates the distributions of dopant concentrations and the distribution of a carrier concentration in the depth direction, which are both measured along the line X-X′ in FIG.
10
. In general, the conductivity type of a particular semiconductor region is determined as p- or n-type depending on the result of comparison in concentration between p- and n-type dopants existing in the particular semiconductor region. That is to say, if the concentration of the p-type dopant is higher in that region than that of the n-type dopant, then the conductivity type of the semiconductor region is p-type, and vice versa. It should be noted that the higher the concentration of an n-type dopant, the lower the ON-state resistance of a MOSFET.
Next, the ON- and OFF-state operations of this semiconductor device will be described.
The p-type buried region
102
is reverse-biased relative to the extended drain region
103
. Accordingly, while this MOSFET is in its OFF state, a depletion layer expands not only from a pn junction between the p-type buried region
102
and the n-type extended drain region
103
, but also from a pn junction between the p-type silicon substrate
104
and the n-type extended drain region
103
. By utilizing these depletion layers, the breakdown voltage of this MOSFET can be increased.
On the other hand, while the MOSFET is in its ON state, electrons are moving through the extended drain region
103
. More specifically, the electrons are moving through part of the extended drain region
103
near the surface of the p-type silicon substrate
104
, where the concentration of the n-type dopant is the highest, and through another part of the extended drain region
103
under the p-type buried region
102
. Thus, this structure can decrease the ON-state resistance of the MOSFET with the breakdown voltage thereof increased. However, if the p-type buried region
102
has been formed by an ordinary diffusion process, then the conductivity type of the surface region of the p-type silicon substrate
104
, where the concentration of the n-type dopant is usually the highest, is inverted into p-type. As a result, the concentration of n-type carriers decreases and the ON-state resistance increases in that region.
The method disclosed in Japanese Laid-Open Publication No. 4-107877 includes the steps of: forming the extended drain region
103
by implanting dopant ions into the p-type silicon substrate
104
and diffusing the dopant through the p-type silicon substrate
104
; implanting boron ions into the extended drain region
103
and then conducting a heat treatment; and thermally oxidizing the surface of the p-type silicon substrate
104
. As a result of the final thermal oxidation process step, the concentration of the p-type dopant in the region between the p-type buried region
102
and the surface of the p-type silicon substrate
104
decreases, thus inverting the conductivity type of that region into n-type. During this thermal oxidation process step, the boron ions, existing in the region above the p-type buried region
102
, are introduced into the silicon dioxide film
105
by utilizing the difference in coefficient of segregation between silicon and silicon dioxide. As a result of this thermal oxidation, the p-type buried region
102
is located at a distance from the surface of the substrate with the thin n-type region interposed therebetween. That is to say, the p-type buried region
102
is embedded in the extended drain region
103
so to speak. However, in order to invert the conductivity type of the region above the p-type buried region
102
into n-type by decreasing the concentration of boron in that region, a thermal oxide film with a relatively large thickness (e.g., 1 &mgr;m or more) should be formed thereon.
In this conventional method, the depth of the p-type buried region
102
from the surface of the substrate and the control over the carrier concentration in the region between the p-type buried region
102
and the surface of the substrate are both dependent on the conditions under which the thermal oxide film
105
is formed. Accordingly, the carrier concentration in that surface region of the extended drain region
103
is affected by a variation in process parameters, including temperature and flow rate of oxygen gas, during the process step of forming the thermal oxide film
105
. More specifically, the surface carrier concentration in the extended drain region
103
is very sensitive to, or greatly variable with, a rate at which the thermal oxide film
105
is formed and with the final thickness of the thermal oxide film
105
. Accordingly, it is extremely difficult to precisely control the surface carrier concentration of the extended drain region
103
during the thermal oxidation process step.
As shown in
FIG. 11
, in the surface region of the semiconductor substrate, the concentration of the p-type carriers is only slightly different from that of the n-type carriers. The difference is so small that this delicate concentration balance is easily disturbed by various factors during the fabrication process. For example, if the concentration of the p-type carriers does not sufficiently decrease in that surface region during the formation of the p-type buried region
102
, then the conductivity type at the surface of the p-type diffusion layer might not be completely inverted into n-type. Or even if the conductivity type has been successfully inverted into n-type, the concentration of the p-type carriers in the surface region may be greatly variable every time the p-type buried region
102
is formed. Such inconsistent inversion or greatly variable concentration is likely to broaden the range of variation in ON-state resistance (e.g., 1.2 to 2.0&OHgr; per unit area) depending on the current passing through the extended drain region between the gate and drain electrodes, or considerably varies the characteristics of the device.
To reduce this variation, a method shown in
FIGS. 12A and 12B
may be employed. In the illustrated method, an extended drain region
26
is first formed within a
Matsushita Electric - Industrial Co., Ltd.
Nguyen Tuan H.
Nixon & Peabody LLP
Robinson Eric J.
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