Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-18
2001-02-20
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S625000
Reexamination Certificate
active
06191023
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of aluminum pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking via structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.
As a background to the current invention, with the continuous shrinking of device dimensions, copper has been the most attractive material for interconnects. Before packaging of the chip, wire bonding is a serious problem when using gold wire bonding directly to a copper pad. Tantalum nitride has been commonly used as the barrier material for copper metallization in combination with an aluminum wire bond pad structure. A “standard” damascene process is used with copper interconnect metallization and large copper pad contacts to tungsten plugs. For better adhesion, the “convention” solution is the addition of tantalum nitride, TaN, as a barrier layer and the deposition of an AlCu pad on the surface. However, using this method is only a partial solution to the wire bonding problem. This invention describes a new method for improved wire bond pad adhesion in which a special via hole interlocking structure is fabricated between the TaN barrier layer and Al pad structure.
2. Description of Related Art
The present invention is a new and improved method for fabricating aluminum metal bond pad structures wherein specifically to the formation of aluminum bond pad metal structures are described which improve adhesion among the tantalum nitride pad barrier layer, top aluminum and the underlying copper pad metallurgy by using a special interlocking via structure. Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,700,735 (Shiue et al.) teaches the formation of via plugs between the top metal layer and the pad. A bond pad structure and method of forming the bond pad structure is described which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45 degrees with respect to the square metal pads.
U.S. Pat. No. 5,707,894 (Hsiao) teaches the formation anchor pads under the pad for better adhesion properties. A structure and a process for forming an improved bonding pad is described which resists bond pad peeling of between the bonding pad layer and the underlying layer. The method comprises forming plurality of anchor pads on said substrate surface in a bonding pad area. Next, a first insulating layer is formed over said substrate surface and the anchor pads. Vias are formed through the first insulating layer. The vias are filled with a second metal layer making a connection to the anchor pads and the first insulating layer is covered in the bonding pad area with the second metal layer. It is important that the via holes have a smaller cross sectional area than the anchor pads so that the combination of the anchor pads and the second metal form small “hooks” into the first insulating layer that hold the second metal (bonding pad layer) to the underlying layer.
U.S. Pat. No. 5,807,767 (Fu et al.) teaches a method of forming a pad with reduced electrical leakage. A method is described for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.
U.S. Pat. No. 5,834,365 (Ming-Tsung et al.) describes a method to form contour stripes under the Al pad layer to create an irregular surface. A structure and a process for forming an improved bonding pad is described which allows for better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.
U.S. Pat. No. 5,309,025 (Bryant et al.) describes conductive lines under the pad which form an irregular pad surface to improve bond pad adhesion. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.
U.S. Pat. No. 5,904,565 (Nguyen et al.) describes an interconnect process with multiple conductive and non-conductive barrier layers. A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.
U.S. Pat. No. 5,795,796 (Kim) shows an Al interconnect with a TaN barrier layer. A method of fabricating a metal line includes the steps of preparing a semiconductor substrate, depositing a first metal on the semiconductor substrate, heat-treating the first metal to form a first metal nitride layer. depositing a second metal on the fir
Ackerman Stephen B.
Potter Roy
Saile George O.
Taiwan Semiconductor Manufacturing Company
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