Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-27
2001-10-16
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S666000, C438S637000
Reexamination Certificate
active
06303496
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly the formation of insulating materials between tightly spaced structures, where a contact hole may be formed.
BACKGROUND OF THE INVENTION
Many types of integrated circuits are fabricated using layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) are formed. Such active devices are then connected to one another by one or more conductive or semiconductive layers (referred to herein as “conducting layers”). The interconnecting conducting layers are separated from one another by insulating layers. Insulating and conducting layers are typically deposited according to a predetermined deposition “recipe” which may define the various materials, conditions and environment used to deposit a layer. Recipes may also be used to etch or pattern an insulating or conducting layer. For example, an etch recipe may be used to form contact holes in an insulating layer, while another set of recipes may be used to pattern a conducting layer.
Conducting layers may be composites of one or more conductive (or semiconductive) materials. As just a few examples, a conducting layer can include a first layer of conventionally doped polycrystalline silicon (polysilicon) and a second layer of “silicide” (silicon-metal alloy). Alternatively, a conducting layer can include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TiN), or a Ti alloy, to name just a few. Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a “doped” silicon dioxide (“oxide”) and an “undoped” silicon oxide. The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide will be essentially free of dopant elements.
Composite insulating layers and/or conducting layers can be undesirable as an increase in the number of layers used to form an integrated circuit generally results in a corresponding increase in the complexity and cost of the fabrication process. For example, a larger number of layers may result in a larger number of layer formation steps, and an increase in the “cycle time” (the time required to process a batch of wafers on which the integrated circuits are formed).
An insulating layer may perform a variety of functions in an integrated circuit. For example, an insulating layer may serve to electrically isolate one conducting layer or structure from another. Further, an insulating layer may serve as the surface on which subsequent layers are formed and patterned. Therefore, in many cases it is desirable for an insulating layer to provide a relatively planar surface. Planar surfaces are more desirable than non-planar surfaces, as typical, conventional lithographic patterning processes provide better results the more planar the surface. As just one example, certain photolithographic techniques using photoresist for producing relatively small structures can have more restricted fields of focus. If a layer on which photoresist is deposited is not planar, the photoresist may not adequately transfer the desired etch pattern. It is thus desirable to provide insulating layers with planar surfaces.
Connections between conducting layers may be made by structures referred to as contacts and “vias.” A typical contact and/or via is formed by etching a hole through one or more insulating layers, and then filling the hole with a conductive or semiconductive material. One concern with certain contact structures is the alignment of the contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conducting layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer.
Another concern regarding the formation of contacts is the etch process that is used to form a contact hole. In the event a contact hole is etched through a composite insulating layer, the etch process may include a different recipe for each of the different insulating materials in the composite layer. This can also increase cycle time and/or add to the complexity of the fabrication process.
Yet another concern regarding contacts and/or vias is the area of the contact. The area of a contact to a substrate can be of particular concern, as the substrate surface area also forms other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or wells.
To better understand the formation of certain integrated circuit structures, including contacts, a conventional self-aligned contact (SAC) approach is set forth in FIGS.
7
and
8
A-
8
I.
FIG. 7
is a flowchart illustrating the general steps involved in forming a self-aligned contact for an integrated circuit that includes metal-oxide-semiconductor (MOS) transistors.
FIGS. 8A-8I
set forth a number of side cross-sectional views of a portion of an integrated circuit following the various steps described in FIG.
7
.
The process set forth in
FIG. 7
is designated by the general reference character
700
, and begins by forming MOS field effect transistor (FET) gate structures (step
702
). A portion of an integrated circuit following step
702
is set forth in FIG.
8
A. MOSFET gate structures
800
are formed on a gate oxide layer
802
. The gate oxide layer
802
is formed on a substrate
804
. The MOSFET gate structures
800
include conductive portions
806
and insulating portions
808
. In order to form as small a transistor as possible, the MOSFET gate structures
800
are patterned to have a desired minimum length (shown in the horizontal direction in FIG.
8
A). Similarly, the distance between adjacent conductive portions
806
is likewise made as small as possible. Consequently, gate length and minimum spacing between adjacent conductive portions
806
may represent the patterning limits of an etch process. Minimum structure widths and structure separations, which may affect the overall operation of an integrated circuit, are often considered “critical dimensions” (CDs) that should be monitored during and/or after the fabrication of an integrated circuit to ensure proper performance. A substrate
804
may have wells formed therein by a previous substrate doping step. A substrate
804
may also include isolation structures formed therein by a previous substrate isolation structure forming step.
As set forth in
FIG. 8B
, following the formation of gate structures
800
, diffusion regions
812
may be formed by doping the substrate
804
with predetermined dopants, usually to form p-n junctions. Such a doping step may include a source and/or drain doping step (which can include ion implantation and subsequent annealing steps) that can be used to form lightly doped diffusion structures, such as lightly doped drains (LDDs).
The process
700
continues by forming sidewalls on the gate structures (step
704
). A portion of an integrated circuit following step
704
is set forth in FIG.
8
B. Sidewalls
810
include insulating structures, and are shown to be formed on the sides of the gate structures
800
. A conventional approach to forming sidewalls
810
includes forming an insulating layer over the gate structures
800
, and subsequently anisotropically etching the insulating layer
Additional doping of diffusion regions
812
may occur following the formation of sidewalls
812
. As just one example, a subsequent diffusion step (which can also include ion implantation and subsequent annealing steps) may be used to form diffusion structures, such as transistor sources and/or drains.
An important aspect of forming diffusion regions
812
is controlling their depth and/or lateral extent. Subjecting a diffusion region to temperature cycles following their initial formation can result in the dopants of the diffu
Cypress Semiconductor Corporation
Picardat Kevin M.
Sako Bradley T.
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