Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-19
2001-11-13
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S592000, C438S595000, C438S527000
Reexamination Certificate
active
06316321
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of MOSFET, and more particularly to a method for forming spacer of a gate.
2. Description of the Prior Art
It has been determined that hot-carrier effects will cause unacceptable performance degradation in NMOS devices built with conventional drain structures if their channel lengths are less than 2 &mgr;m. To overcome this problem, such alternative drain structures as lightly doped drains (LDDs) must used.
In the LDD structure, the drain is formed by an implant self-aligned to the gate electrode, and the other is self-aligned to the gate electrode against which an oxide spacer has been formed. The purpose of the lighter first dose is to form a lightly doped section of the drain at the edge near the channel. In NMOS devices, this dose is normally 1-2×10
13
atoms/cm
2
of phosphorus.
In the conventional fabrication of MOSFET, to form a gate, resist and etching are used after the metal-oxide-semiconductor (MOS) layer is deposited. Unfortunately, solvent used to strip the resist will erode the sidewall of the gate to lead to a narrower width and higher electric resistance. In the following implantation for LDD, the exposing sidewall of the gate is attacked by the ions going to be implanted into the substrate. The emancipated metal particles, such as Ti, will pollute the chamber of machine. Moreover, during the stripping of photoresist used for the LDD implantation, the sidewall of the gate will be eroded, too. Therefore, the quality of products and the efficiency of fabrication will be both reduced.
For the foregoing reasons, there is a need for solving the pollution of machine and the high electric resistance of gates to enhance both the quality of products and the efficiency of fabrication.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming spacer of a gate in fabrication of MOSFET. It could substantially solve the problem of unstable resistance of a gate due to the attack of ions in implanting process. In one embodiment, a substrate, on which there is a gate without spacer, is firstly provided. Then, a first insulating layer, such as oxide, is deposited on the substrate and the gate. Subsequently, etch back the first insulating layer. Ion implantation is used to form a lightly doped drain in the substrate. Therein, implanted ions never pass through the first insulating layer. A liner layer, such as oxide, is formed on the substrate and the first insulating layer to serve as a stop layer of the following etching process. A etching process is used after a second insulating layer such as nitride is formed on the liner layer. Finally, ion implantation is used again to form a heavily doped drain in the substrate.
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Chen Tung-Po
Chou Jih-Wen
Lin Yung-Chang
Goodwin David
Powell Goldstein Frazer & Murphy LLP
United Microelectronics Corp.
Wilczewski Mary
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