MISFET semiconductor device having relative impurity...

Details MISFET semiconductor device having relative impurity... MISFET semiconductor device having relative impurity...

1998-09-16

2001-11-27

Loke, Steven (Department: 1931)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S394000, C257S395000, C257S344000

Reexamination Certificate

active

06323525

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a MISFET and, more particularly, to a semiconductor device having a structure in which part of the source/drain regions is formed above the interface between the substrate and the gate insulating film.
MISFETs suffer a phenomenon, i.e., so-called DIBL (Drain Induced Barrier Lowering) that the threshold voltage drops upon application of the drain voltage. This will be briefly explained using an n-type MISFET in FIG.
1
A.
In
FIG. 1A
, a polysilicon gate electrode
1
doped with B, As, or P is formed via a gate insulating film
2
made of a silicon oxide film on an Si semiconductor layer
7
for forming a channel region. Source and drain regions
3
and
4
of a conductivity type opposite to that of the semiconductor layer
7
are formed on the two sides of the gate electrode
1
by ion-implanting P or As. Insulating films
8
are formed on the two sides of the gate electrode
1
, whereas an insulating film
8
′ is formed on top of the gate electrode
1
.
Assume that the drain region
4
receives a higher voltage than that for the source region
3
. This is the case wherein the n-type MISFET is used to form, e.g., a logic circuit for a static inverter in FIG.
1
B. In
FIG. 1B
, the gate electrode of an n-type MISFET
9
is connected to the gate electrode of a p-type MISFET
9
′ to form an input electrode
10
of the inverter. The drain
4
of the n-type MISFET
9
is connected to the drain
4
of the p-type MISFET
9
′ to form an output
10
′ of the inverter. The source
3
of the n-type MISFET
9
is grounded (0V), and the source of the p-type MISFET
9
′ is connected to a power supply terminal (V
DD
). In this manner, a static inverter is constructed.
When a logic circuit is formed using an n-type MISFET, like this inverter, the voltage applied to the p-n junction between the drain and the substrate is higher than the voltage applied to the p-n junction between the source and the substrate. For this reason, as shown in
FIG. 1A
, a substrate-side edge
5
′ of a depletion layer formed by the p-n junction between the drain and the substrate extends to the semiconductor layer
7
much more than a substrate-side edge
5
″ of the depletion layer defined by the p-n junction between the source and the substrate. That region (charge share region)
6
of the depletion layer, which is below the gate electrode and shared by a drain depletion layer, widens when the drain voltage increases. As a result, the depletion layer that can be controlled by the gate narrows. As the negative charges contained in the gate-controlled depletion layer decrease, the threshold voltage of the transistor lowers. Accordingly, the threshold voltage drops upon application of the drain voltage.
This phenomenon is so-called DIBL. Since the ratio of the charge share region
6
to the overall depletion layer below the gate electrode increases with a decrease in gate length, the drop in threshold voltage becomes prominent as the gate length becomes shorter.
To suppress widening of the charge share region upon application of the drain voltage, it has been found effective to extend the depletion layer to the drain region upon application of the drain voltage and as a result, suppress substrate-side widening of the depletion layer formed in the semiconductor layer
7
. However, when this method is adopted in a simple drain structure in which the drain is formed nearer the substrate than the interface between the substrate and the gate insulating film, the parasitic resistance of the drain increases undesirably. This will be explained using a uniformly doped drain structure in
FIGS. 2A and 2B
.
FIG. 2A
is an enlarged sectional view showing the drain and the substrate when voltages V
BS
and V
D
are respectively applied to the substrate electrode and the drain. Donors are uniformly doped in the drain region
4
at an impurity concentration N
D
, and acceptors are uniformly doped in the semiconductor layer
7
at an impurity concentration N
A
. In this case, using depletion approximation with reference to a charge distribution shown in
FIG. 2B
corresponding to the section taken along the line A-A′ in
FIG. 2A
, a distance X
n
from the boundary between the drain region
4
and the semiconductor layer
7
to the edge of the depletion layer extending to the drain region is given by:
X
n
={2&egr;
S
(
V
D
+V
BI
−V
BS
)/
q}
0.5
×{N
A
/N
D
/(
N
A
+N
D
)}
0.5
  (1)
where &egr;
S
is the dielectric constant of the semiconductor, and q is the elementary charge, V
BI
is the built-in voltage.
From equation (1), X
n
monotonically decreases with increasing N
D
. The upper limit of the impurity amount which can be doped to the semiconductor is determined by the solid solubility limit. Letting N
Dmax
be the upper limit of the donor impurity amount, the lower limit X
nmin
of X
n
is given from equation (1) by:
X
nmin
={2&egr;
S
(
V
D
+V
BI
−V
BS
)/
q}
0.5
×{N
A
/N
Dmax
/(
N
A
+N
Dmax
)}
0.5
  (2)
Further, when
y
represents the drain length, W represents the channel width, X
j
represents the formation depth of the drain region in
FIG. 2A
, and &rgr; represents the resistivity, the resistance R of the drain is
 
R=y&rgr;/{W
(
X
j
−X
n
)}  (3)
Since &rgr; monotonically increases with N
D
, the relation of R for X
n
shown in
FIG. 3
can be obtained using equations (2) and (3). From equation (2), as X
n
comes closer to X
j
, R diverges infinitely. That is, when X
n
is increased to suppress widening of the charge share region by extending the depletion layer to the drain region, the resistance of the drain increases infinitely if X
j
remains constant. From equation (2), since X
nmin
is a constant that is determined regardless of X
j
, the allowable range of X
n
narrows with decreasing X
j
. If X
n
varies due to variations in impurity concentration and defect distribution, the parasitic resistance of the drain also varies. Consequently, the drivability varies between devices, and thus the delay time of the logic circuit varies, which makes it difficult to design a high-speed optimum operation.
According to the study made by the present inventors, such an increase in parasitic resistance can be effectively prevented by a so-called elevated (to be referred to as EV hereinafter) source/drain structure like the one shown in
FIG. 4A
in which at least part of the source/drain regions is formed above the interface between the substrate and the gate insulating film. This EV source/drain structure itself is described in, e.g., S. Nishimatsu, Y. Kawamoto, H. Masuda, R. Hori, and O. Minato, “Grooved Gate MOSFET”, Jpn, J. Appl. Phys., 16; Suppl. 16-1, 179 (1977).
The structure in
FIG. 4A
is basically the same as that in
FIG. 1A
except that the source and drain regions
3
and
4
are formed above the interface between the semiconductor layer
7
and the gate insulating film
2
. A source contact formation region
3
′ and a drain contact formation region
4
′ are respectively formed X
1
apart from gate insulating film
2
′ in the source region
3
and the drain region
4
. The broken lines in
FIG. 4A
indicate the edges of a depletion layer formed in the source and drain regions
3
and
4
and the semiconductor layer
7
. The thickness of the gate insulating film
2
between the gate electrode
1
and the semiconductor layer
7
is equal to or smaller than the thickness of a gate insulating film
2
′ between the gate electrode 1 and the source region
3
.
In the EV source/drain structure, letting
y
be the distance from the upper surface of the doped drain layer to the depletion layer, W be the channel width, X
1
be the length of the drain region
4
measured from the drain contact region
4
′, and &rgr; be the resistivity, as shown in
FIG. 4A
, the parasitic resistance R from the upper edge of the dra

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