Semiconductor transistor devices and methods for forming...

Details Semiconductor transistor devices and methods for forming... Semiconductor transistor devices and methods for forming...

1998-10-06

2001-11-20

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S200000

Reexamination Certificate

active

06319779

ABSTRACT:

TECHNICAL FIELD
This patent pertains to methods of forming graded junction regions operatively adjacent transistor gates, methods of forming graded junction regions operatively adjacent transistor gates of CMOS circuitry, and methods of forming graded junction regions operatively adjacent peripheral NMOS transistor gates and operatively adjacent the transistor gates of a memory array. The patent also pertains to semiconductor transistor devices generally.
BACKGROUND OF THE INVENTION
This invention grew out of a need to improve the methods of implanting graded junction regions within semiconductor devices and to thereby enhance production of integrated circuitry. Some typical types of graded junction regions are described with reference to FIG.
1
.
In
FIG. 1
is shown a semiconductor wafer fragment
10
comprising a portion of a semiconductor wafer material
12
. Wafer
12
comprises an upper surface
13
. Preferably, the semiconductor material of wafer
12
comprises conductively doped polysilicon. Above and within semiconductor wafer
12
is formed a transistor device
14
. Device
14
comprises a gate
16
, source/drain regions
18
, and graded junction regions
20
and
22
.
Gate
16
further comprises a gate oxide layer
24
, a polysilicon layer
26
, a refractory metal layer
28
, an upper oxide layer
29
, and a cap layer
30
. Refractory metal layer
28
typically comprises a metalsilicide, such as tungsten silicide or titanium silicide, and cap layer
30
preferably comprises silicon nitride.
Gate
16
also comprises opposing lateral sidewalls
32
. Sidewall spacers
34
are adjacent sidewalls
32
and comprise a sidewall spacer material, preferably silicon nitride. Sidewall spacers
34
comprise a lateral thickness “X”, which as measured at about the height of metal layer
28
is typically from about 200 Angstroms to about 1000 Angstroms.
Also, adjacent lateral sidewalls
32
is a silicon oxide layer
36
. Silicon oxide layer
36
is generally formed by oxidizing the polysilicon of gate
16
and the polysilicon of upper surface
13
of wafer
12
.
Source/drain regions
18
contain a conductivity enhancing dopant of a type dictated by the type of transistor device
14
. If transistor device
14
is a P-channel Metal-Oxide Semiconductor (PMOS) field effect transistor, then source/drain regions
18
will comprise a p-type dopant. If, on the other hand, transistor device
14
is an N-channel Metal-Oxide Semiconductor (NMOS) field effect transistor, source/drain regions
18
will comprise n-type dopant.
Graded junction regions
20
and
22
are typically lightly doped drain (LDD) regions and halo regions. Generally, and preferably, the graded junction region extending nearest to gate
16
, i.e., region
22
, will be a halo region and the other graded junction region, i.e., region
20
, will be an LDD region. However, the order of the graded junction regions can be reversed. Also, one or both of the graded junction regions may be eliminated in various transistor devices.
The LDD regions comprise conductivity enhancing dopant of the same conductivity type as the adjacent source/drain regions. Thus, in an NMOS device the LDD regions comprise ntype dopant and in a PMOS device the LDD regions comprise p-type dopant. The LDD regions reduce the electric field under gate
16
and thereby reduce the energy of hot electrons within transistor device
14
. Such reduction in energy can reduce the damage caused to device
14
by hot electrons.
The halo regions comprise conductivity enhancing dopant of a different conductivity type than the adjacent source/drain regions. Thus, in an NMOS device the halo regions comprise a p-type dopant and in a PMOS device the halo regions comprise n-type dopant. The halo regions are used to improve the punch-through resistance of transistor device
14
.
Referring to
FIG. 2
, a semiconductor wafer fragment
40
is illustrated at a processing step in accordance with the prior art. Fragment
40
comprises a portion of semiconductor wafer material
42
. The semiconductor material of wafer
42
preferably comprises conductively doped polysilicon. The shown wafer fragment
40
is subdivided into three defined regions: PMOS region
44
(only a portion of which is shown), peripheral NMOS region
46
, and memory array region
48
(only a portion of which is shown). Regions
44
and
46
together comprise a defined peripheral region
50
(only a portion of which is shown).
The semiconductor material of wafer
42
within peripheral NMOS region
46
and memory array region
48
is typically polysilicon lightly doped with a p-type impurity. The semiconductor material of wafer
42
within PMOS region
44
is typically polysilicon comprising a well
52
which is lightly doped with an n-type impurity.
A series of transistor gates
54
,
56
,
58
and
60
are provided on a top surface
61
of wafer
42
. Gate
54
corresponds to a PMOS transistor gate, gate
56
corresponds to a peripheral NMOS transistor gate, and gates
58
and
60
correspond to memory array NMOS transistor gates. Also shown are field oxide regions
62
between the transistor gates and a word line
64
(only a portion of which is shown) over one of the field oxide regions. Gates
54
,
56
,
58
and
60
, as well as word line
64
, all comprise a gate oxide layer
66
, a polysilicon layer
68
, a refractory metal layer
70
, an upper oxide layer
71
, and a cap
72
, as was described previously regarding transistor device
14
. Further, each of gates
54
,
56
,
58
, and
60
, as well as word line
64
, comprise opposing lateral sidewalls
63
.
A prior art processing method of forming graded junction regions for the circuitry of
FIG. 2
is described with reference to
FIGS. 3-6
.
Referring to
FIG. 3
, n-type regions
74
and
76
are implanted into peripheral and memory NMOS regions
46
and
48
respectively. Regions
74
are peripheral NMOS LDD regions implanted operatively adjacent peripheral NMOS gate
56
, while regions
76
are memory array source/drain regions implanted operatively adjacent memory array NMOS gates
58
and
60
. As the memory array source/drain regions
76
are typically implanted at a dopant concentration and depth comparable to the peripheral NMOS LDD regions
74
, regions
74
and
76
are typically implanted during a common implant step.
Also referring to
FIG. 3
, p-type LDD regions are implanted operatively adjacent PMOS gate
54
to form PMOS LDD regions
78
.
After the implant of regions
74
,
76
, and
78
, the polysilicon of gates
54
,
56
,
58
and
60
as well as of word line
64
and upper surface
61
is oxidized to form the silicon oxide layer
80
.
Referring to
FIG. 4
, a first masking layer provision step occurs as PMOS region
44
and memory array region
48
are covered with a masking layer
82
, preferably of photoresist. Subsequently, a p-type dopant
84
is implanted into peripheral NMOS region
46
to form peripheral NMOS halo regions
86
operatively adjacent peripheral NMOS gate
56
. Halo regions
86
are displaced further from gate
56
than LDD regions
74
as a result of LDD regions
74
being implanted prior to formation of oxide layer
80
and halo regions
86
being implanted subsequent to formation of oxide layer
80
.
Referring to
FIG. 5
, masking layer
82
is removed and subsequently sidewall spacers
88
,
90
,
92
,
94
and
96
are provided adjacent gates
54
,
56
,
58
,
60
and word line
64
, respectively.
Referring to
FIG. 6
, a second masking layer provision step occurs as PMOS region
44
and memory array region
48
are again masked, this time with a masking layer
98
, preferably of photoresist. Subsequently, n-type dopant
100
is implanted into peripheral NMOS region
46
to form peripheral NMOS source/drain regions
102
operatively adjacent peripheral NMOS gate
56
. Source/drain regions
102
are displaced further from gate
56
than graded junction regions
74
and
86
as a result of source/drain regions
102
being implanted subsequent to provision of sidewall spacers
90
and graded junction regions
74

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