Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-10
2001-12-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S302000, C257S304000, C257S305000, C257S306000, C438S242000, C438S243000, C438S268000, C438S386000
Reexamination Certificate
active
06333533
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories (DRAM's) and, more particularly, to trench capacitor construction.
2. Background Description
As dynamic random access memory cells are scaled down (e.g., to dimensions of 0.15&mgr; and below) to meet chip-size requirements for future generations, planar (i.e., horizontally disposed) devices can no longer be used as transfer devices. Such use is precluded because of the high channel doping necessary to meet the off-current requirement which leads to high junction leakage and poor retention time, particularly with a trench storage DRAM cell using a buried strap. Vertical transfer devices have been proposed to overcome the problem.
Vertical transfer devices generate, however, a new set of problems. For example, back-to-back device interference is created. In addition, the depth of the storage trenches and the shallow trench isolation must increase to accommodate a long channel of the vertical transfer. This increased depth complicates the fabrication process and adds to the cost of the product. Another problem is increased substrate sensitivity due to high doping required to minimize back-to-back interference. Furthermore, the long channel required for improved threshold voltage tolerance due to channel length variations due to the manufacturing process results in a penalty in the on-current. Yet another problem is variable channel surface geometry and gate oxide thickness because of the overlay variations between the silicon of the vertical metal oxide semiconductor field effect transistor (MOSFET) and storage trench regions.
To overcome the problems of conventional vertical DRAM cells, a new trench storage DRAM cell is provided having a vertical three-sided transfer device. It is an object of the present invention to provide a new and improved vertical transfer device that is built on top of a deep trench storage node and is compatible with contemporary DRAM process steps. It is another object of the present invention to provide dynamic random access memory cells that have increased on-current of the vertical MOSFETs. It is a further object of the present invention to provide dynamic random access memory cells that have channel regions of increased length in the active area which improves the threshold voltage tolerance. Still another object of the present invention is to provide dynamic random access memory cells that have flexibility in setting the length of the channel regions in the active area. Yet another object of the present invention is to provide dynamic random access memory cells which, because of the shapes and sizes of the trenches and the active area, reduce the risk associated with misalignment of the trenches and active area which can lead to variations in electrical characteristics.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a pair of dynamic random access memory cells. As constructed in accordance with the present invention, the pair of DRAM cells includes a substrate having first and second deep trenches separated by an active area defined by a first end at a sidewall of the first deep trench and a second end at a sidewall of the second deep trench. The pair of DRAM cells also includes a first diffusion region (1) in the active area, (2) extending between an upper portion of the first deep trench and an upper portion of the second deep trench, and (3) connected to a bitline. The pair of DRAM cells further includes a second diffusion region in the active area and adjacent the sidewall of the first deep trench, whereby a first channel region is created in the active area between the first diffusion region and the second diffusion region, and a third diffusion region in the active area and adjacent the sidewall of the second deep trench, whereby a second channel region is created in the active area between the first diffusion region and the third diffusion region.
The pair of dynamic random access memory cells, constructed in accordance with the present invention, further includes first and second storage node electrodes in lower portions of the first deep trench and the second deep trench, respectively; first and second storage plates surrounding lower portions of the first deep trench and the second deep trench, respectively; and first and second dielectric members, respectively, between the first storage node electrode and the first storage plate and between the second storage node electrode and the second storage plate. The pair of dynamic random access memory cells, constructed in accordance with the present invention, also includes a first gate conductor (a) in the upper portion of the first deep trench, (b) surrounding the first end of the active area in the substrate, and (c) connected to a first wordline for controlling current in the first channel region between the first diffusion region and the second diffusion region. A second gate conductor is provided (a) in the upper portion of the second deep trench, (b) surrounding the second end of the active area in the substrate, and (c) connected to a second wordline for controlling current in the second channel region between the first diffusion region and the third diffusion region. Also included in the pair of dynamic random access memory cells, constructed in accordance with the present invention, are a first isolation collar on the walls of the upper portion of the first deep trench extending between the first storage plate and the second diffusion region, a second isolation collar on the walls of the upper portion of the second deep trench extending between the second storage plate and the third diffusion region, and first and second buried straps, respectively, connecting the first storage node electrode with the second diffusion region and the second storage node electrode with the third diffusion region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 5831301 (1998-11-01), Horak et al.
patent: 6037194 (2000-03-01), Bronner et al.
patent: 6184549 (2001-02-01), Furukawa et al.
patent: 2-62070-A (1990-03-01), None
patent: 4-61273-A (1992-02-01), None
Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Kanarsky Thomas S.
International Business Machines - Corporation
Kang Donghee
Ratner & Prestia
Shkurko, Esq. Eugene I.
Thomas Tom
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