Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate
1999-11-23
2001-10-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
C326S102000, C326S103000
Reexamination Certificate
active
06297668
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, the present invention relates to techniques for providing improved flip-flops, latches, and other logic circuits, and techniques for improving the layouts of such circuits.
BACKGROUND OF THE INVENTION
Flip-flops are the general-purpose data storage element used in digital electronic circuitry. Flip-flops are important to the design of digital circuits, because they are the general-purpose clocked storage elements that make sequential and state logic design feasible. Some of the uses of flip-flops include storage of logic states, parameters, and digital control signals. Microprocessors, for example, typically contain thousands of flip-flops. A few well-known types of flip-flops include D, set, reset, set-reset, JK, toggle enable, and scan type flip-flops.
Because flip-flops may affect the integrated circuits in which they are used, it is highly desirable to improve their design and performance. Flip-flops may affect the integrated circuits in which they are used in the following ways:
1. The switching speed of flip-flops is a fundamental limiting factor of logic circuits. Flip-flop setup and hold times along with clock-to-output times are fundamental limits in setting the maximum logic clocking speed. Because the setup and hold times to store a logic 0 value or a logic 1 value are different, it is generally desirable to minimize the difference in order to reduce the overall switching time of the flip-flop.
2. Flip-flops are used to set the basic design speed of an integrated circuit cell library from which digital circuits are made. The flip-flop maximum toggle rate defines the maximum clock frequency of the library.
3. Flip-flops define the speed and phase noise of digital phase locked loops;
4. The time gap between the latest usable setup time and the subsequent earliest hold time defines a metastable window. Reducing the length of this metastable window improves the performance of state logic and other synchronous applications.
5. The flip-flop layout configuration defines the cell “height” (rail-to-rail distance) of an entire integrated circuit cell library. An asynchronously resetable edge-triggered data flip-flop is perhaps the most often used large cell in a digital library. Reducing the digital library cell height, as determined by the flip-flop height, directly reduces the chip area and results in less interconnect parasitic effects.
6. The transient power consumption of a flip-flop is instrumental in setting the width of the power busses required in the cell library's layout so that adequate power can be supplied for a given transient voltage drop.
7. The energy a flip-flop consumes during toggling and the load it places on the clock input line is a significant contributor to the overall circuit power dissipation.
8. The flip-flop switching speed defines the time window in which transient current passes through its complementary switching devices. Faster switching produces less pass through charge for lower power operation. Low activity within the flip-flop when it is clocked but not toggled also reduces power consumption.
9. Race conditions during flip-flop toggling add to the pass-through current. Eliminating the race tends to eliminate the current component.
10. Switched capacitance internal to the flip-flop is a major transient current component. A flip-flop in which switched capacitance is minimized has less switching current while achieving high switching speeds.
11. The ratio of the transistor switching strength to the amount of the switched parasitic capacitance determines the flip-flop's internal speed.
12. A small number of series gate delays from the data (D) input of a flip-flop to the output (Q) is desirable for fast setup and hold times. A small number of series gate delays from clock (CK) to output (Q) provides fast flip-flop response time.
13. A balance in the delay paths from the data (D) and clock (CK) inputs to the output (Q) reduces the asymmetric delay times. The difference between the positive and negative going response times should be included in the flip-flop's switching time specification. It also biases the probability the switching response to random inputs for circuits that synchronize random signals.
14. A small number of series devices driving the output path, especially weaker p-channel devices, increases the output drive and thus reduces transition time.
15. A minimum of two series transistors is required to implement a logic function. By using this number of series transistors as a maximum in a flip-flop, its power, speed, area, and low voltage performance are improved.
16. The low voltage performance of a flip-flop generally defines the minimum operating voltage of logic circuitry. This not only allows low voltage operation, but greatly saves power dissipation by a square law given by P~V
2
.
17. The static power dissipation of ultra low power integrated circuits is from the “off” state leakage current of the metal-oxide semiconductor (MOS) transistor leakage currents as well as the MOS diffusion areas. It is desirable to minimize these parameters.
18. Advanced flip-flop configurations can simplify the logic that is connected to them. This extends the logic circuit operation and functionality and reduces the delay and total area consumed.
For these and other reasons, it is desirable to have improved flip-flop configurations and design techniques and related digital logic circuitry.
Flip-flops are generally made of latches. Latches typically form the master or slave half of an edge-triggered flip-flop, or both. Thus, a flip-flop is often constructed from a master latch and a slave latch, in which the output of the master latch is the input of the slave latch, and the output of the slave latch provides the output of the flip-flop. Instead of being edge-sensitive to the clock control input, latches are level sensitive to a clock equivalent control input customarily called “enable.” When the enable control signal is active, the latch accepts the logic-input signal on the data line. During this time, the data input signal is passed through to the output Q, which is known as the pass-through state of the latch. When the enable control signal is in the inactive condition, the data input line is locked out of the latch, and the Q output reflects the logic state contained in the latch at the time the enable signal was taken low. Latches have a similar impact as flip-flops on the integrated circuits in which they are used. They are often used in an array such as a register file, where they have a special data path layout that shares resources. Special design and layout considerations enhance their use in this.
FIG. 1
shows a very simple form of a static latch cell, which is a pair of cross-coupled inverters. Overdriving the latch outputs, using additional transistors, performs the set and reset control. This approach with address selection transistors can be used to form static Random Access Memory (RAM) cells.
FIG. 2
shows a Set-Reset latch formed by replacing the inverters of
FIG. 1
with NOR logic gates. Replacing the inverters with NAND logic gates forms an active-low SetN-ResetN cross-coupled latch. Note that with respect to the Q and Qn outputs, the NAND gate SetN and ResetN inputs are on the opposite gates from the NOR gate Set-Reset latch.
The design of the flip-flop is the fundamental starting point of an integrated circuit library. First, the desired speed/power-consumption tradeoff is chosen. The flip-flop is then designed to meet this criterion using an estimated output loading. This output loading is based on the routing complexity and the expected integrated circuit core size. The proportions of the flip-flop and other cell sizes, which are being designed in this process, set this in turn. Iterative processes of estimation, simulation, and back-annotation are used to arrive at the solution. Through the cell library design, the speed and power consumption are set, and thus, the speed and power
Becker Jordan M.
Blakely , Sokoloff, Taylor & Zafman LLP
ManoPower Technologies, Inc.
Tokar Michael
Tran Anh Q.
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