Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-09
2001-12-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S621000, C438S622000, C438S647000, C438S649000, C438S655000, C438S656000, C438S657000, C438S660000, C438S664000, C438S680000, C438S681000, C438S682000, C438S683000, C438S684000, C438S685000
Reexamination Certificate
active
06329283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the method of fabricating a semiconductor device, and more particularly to the method of fabricating a self-align-contact by using self-align silicide (Salicide) process.
2. Description of the Related Art
In the semiconductor process there are many methods of fabricating a self-align-contact. One of the conventional methods of forming a self-align-contact includes first providing a substrate on which there are at least two MOS devices and then forming an insulating layer, such as silicon oxide, on the substrate. Each of the two MOS devices includes a polysilicon gate and spacers on the sidewalls of the gate. The two MOS devices have a common source/drain region located between the gates of the two MOS devices. The insulating layer is patterned to form a self-align-contact opening which exposes the common source/drain region. A conductive layer is deposited in the self-align-contact opening to form a contact.
A process flow showing the formation of a conventional self-align-contact is illustrated by
FIGS. 1A-1E
. Referring to
FIG. 1A
, a gate
102
and source/drain regions
110
are formed on a semiconductor substrate
100
. The gate
102
includes a gate oxide
104
, a doped polysilicon layer
106
and a cap layer
108
. The cap layer
108
is formed over the doped polysilicon layer
106
to protect the doped polysilicon layer
106
. A spacer
112
is formed on the sidewalls of the gate
102
. The source/drain regions
110
are lightly doped drain (LDD) structures. The method of forming the source/drain regions
110
includes lightly implanting ions into the semiconductor substrate
100
using the gate
102
as a mask and heavily implanting ions into the semiconductor substrate
100
using the spacer
112
as a mask. Referring to
FIG. 1B
, a dielectric layer
114
is formed on the semiconductor substrate
100
by CVD.
Next, referring to
FIG. 1C
, the dielectric layer
114
is patterned by both a lithography process and etching to form a contact opening
116
between two gates
102
to expose the source/drain region
110
.
Next, referring to
FIG. 1D
, a conductive layer
120
, such as doped polysilicon, is formed in the contact opening
116
and on the semiconductor substrate
100
by deposition.
Referring to
FIG. 1E
, a conductive layer
122
, such as metal silicide, is deposited on the conductive layer
120
to reduce the resistance of the conductive layer
120
. Then the conductive layer
120
and the conductive layer
122
are patterned by both a lithography process and etching to form a self-align-contact of prior art.
In the integrated circuits (IC) process, the conventional method of fabricating a self-align-contact includes many drawbacks. For example, the resistance of the self-align-contact is very large and such high resistance can not meet the needs of current integrated circuits with high operation speed.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of fabricating a self-align-contact by using a salicide process.
It is another object of the invention to provide a simple method of fabricating a self-align-contact with low resistance and that is able to make good ohmic contact.
It is an object of the invention to provide a method of fabricating a self-align-contact to meet the needs of current integrated circuits with high operation speed.
A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. Spacers are formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacers, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the surface of the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.
REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 5094981 (1992-03-01), Chung et al.
patent: 5480837 (1996-01-01), Liaw et al.
Niebling John F.
United Microelectronics Corp.
Zarneke David A
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