Methods for forming metal interconnects

Details Methods for forming metal interconnects Methods for forming metal interconnects

1999-10-05

2001-10-02

Lee, Eddie C. (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S689000, C438S700000

Reexamination Certificate

active

06297149

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and more specifically to methods for forming metal interconnects within semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
A typical integrated circuit contains a plurality of metal pathways to provide electrical power for powering the various semiconductor devices comprising the integrated circuit, and to allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or “interlayer” dielectrics that insulate the metal layers from each other. Typically, however, each metal layer must form electrical contact to an additional metal layer.
Metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers to be connected, and by filling the resulting hole or via with a metal (creating an “interconnect”). In a conventional dual damascene process, a “line” or trench is first etched in the interlayer dielectric followed by the formation of a via therein (i.e., a line first dual damascene process). Both the line and the via then are filled with a metal to create an interconnect.
Because variations in line density across a semiconductor chip produce thickness variations in the photoresist (“resist”) used to image vias during a line first dual damascene process, the reproducible production of small vias across a semiconductor chip is difficult using conventional line first dual damascene processes. One method for overcoming this problem is to partially or completely etch each via prior to line formation, and to thereafter re-mask, define and etch each line (i.e., a via first dual damascene process). However, removing line imaging resist (and/or anti-reflective coating) from vias is difficult, especially for high aspect ratio vias (e.g., vias having aspect ratios that exceed three). Any residual line imaging resist remaining within a via blocks contact to the underlying metal layer and degrades/inhibits interconnect formation. Accordingly, a need exists for methods for forming improved metal interconnects.
SUMMARY OF THE INVENTION
To address the needs of the prior art, inventive methods for forming metal interconnects are provided. An insulating layer is formed on top of a substrate (e.g., a substrate having a metal line formed therein) and a via is formed in the insulating layer reaching to the substrate. The via then is filled with a sacrificial material and a trench aligned over the via is formed by removing an upper portion of the insulating layer and an upper portion of the sacrificial material within the trench. The sacrificial material preferably is selected to etch faster than the insulating layer. After forming the trench, remaining sacrificial material in the via is removed and the via and the trench are filled with a conductive material.
In addition to a single insulating layer, the insulating layer on top of the substrate may comprise a first insulating layer formed on top of the substrate, an etch stop layer formed on top of the first insulating layer and a second insulating layer formed on top of the etch stop layer. In this manner, the trench aligned over the via may be formed by removing a section of the second insulating layer and an upper portion of the sacrificial material within the trench (e.g., by using the etch stop layer during removal of the section of the second insulating layer). A barrier layer may be formed within the via after via formation and prior to filling the via with a sacrificial material so as to prevent lateral etching of the via during removal of sacrificial material therefrom.
By employing a sacrificial “filler” material within the via, via formation may be performed prior to trench (e.g., line) formation without residual line imaging resist or anti-reflective coating remaining within the via. Therefore, low resistance dual damascene interconnects employing high aspect ratio vias may be reproducibly formed.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.


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