Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-06-30
2001-10-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189120
Reexamination Certificate
active
06304497
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an array of memory cells arranged in addressable blocks, an n-bit status register, and a control circuit coupled to the n-bit status register to program a first bit of the n-bits to a first state indicating if a program operation is being performed on the array. The control circuit further programs second and third bits of the n-bits to identify one of the addressable blocks while the array is being programmed.
In another embodiment, a memory system comprises a memory controller, and a memory device coupled to the memory controller. The memory device comprises an array of memory cells arranged in addressable blocks, an n-bit status register, a plurality of programmable non-volatile registers, and control circuitry coupled to the n-bit status register to program a first bit of the status register to a indicate a programming status of the memory device. The control circuit further programs second and third bits of the status register to identify one of the addressable blocks or one of the plurality of programmable non-volatile registers.
One method of operating a memory device is provided. The method comprises modifying first data stored in a status register of the memory device to a first data state to indicate that a write operation is being performed on the memory device, and modifying second data stored in the status register of the memory device to indicate a location of programmable circuitry in the memory device accessed during the write operation.
Another method of operating a memory device comprises initiating a write operation on a first programmable location of the memory device using a first processor, and reading a status from status data stored in the memory device during the write operation. The status indicates an identification of the first programmable location.
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Dinh Son T.
Fogg Slifer & Polglaze, P.A.
Micro)n Technology, Inc.
Slifer Russell D.
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