Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-15
2001-11-13
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S236000, C438S217000
Reexamination Certificate
active
06316317
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including two-transistor type memory cells and its manufacturing method.
2. Description of the Related Art
In a nonvolatile semiconductor memory device, a write operation can be carried out after the device is mounted on a printed circuit board. One typical example of such a device is a flash memory which has an advantage in that data storage is possible without a backup battery, and which is highly integrated. Generally, one memory cell of the flash memory is formed by a silicon substrate, a floating gate over a channel region of the substrate, and a control gate over the floating gate.
Recently, in order to increase an ON current flowing through the memory cell, two-transistor type memory cells have been developed. A prior art memory cell of this type is formed by one selection transistor and one memory transistor connected in series and controlled by voltages of a pair of word lines, and the thickness of a gate insulating layer of the selection transistor is the same as that of a gate insulating layer of the memory transistor. Also, the threshold voltage of the selection transistor is the same as that of the memory transistor where no charges are injected into a floating gate. This will be explained later in detail.
Generally, the thinner the gate insulating layer, the larger an ON current flowing through each of the selection transistor and the memory transistor. In the memory transistor, however, if the gate insulating layer is too thin, electrons accumulated in the floating gate are leaked through the gate insulating layer into the silicon substrate. Therefore, it is impossible to greatly reduce the thickness of the gate insulating layer for the memory transistor. On the other hand, in the selection transistor, since the floating gate is not provided, it is possible to greatly reduce the thickness of the gate insulating layer for the selection transistor.
Therefore, in the prior art memory cell, it is impossible for the gate insulating layer to be optimum both for the selection transistor and the memory transistor.
Further, if the threshold voltage of the memory transistor where no electrons are injected into the floating gate is too large, a read operation performed upon this memory transistor may invite a soft write operation, which is called a read disturb phenomenon. Therefore, in order to avoid this read disturb phenomenon, it is preferable that the threshold voltage of the memory transistor be smaller.
In the prior art memory cell, however, it is impossible to adjust the threshold voltage of the memory transistor, independent of the threshold voltage of the selection transistor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a two-transistor type nonvolatile memory cell including a gate insulating having an optimum thickness both for a selection transistor and a memory transistor and a method for manufacturing such a memory cell.
Another object is to avoid the read disturb phenomenon in a two-transistor type nonvolatile memory cell.
According to the present invention, in a nonvolatile semiconductor memory device including a plurality of memory cells each formed by one selection transistor and one memory transistor connected in series, the thickness of a first gate insulating layer of the selection transistor is smaller than the thickness of a second gate insulating layer of the memory transistor.
Also, the threshold voltage of the selection transistor is different from the threshold voltage of the memory transistor where no charges are injected into a floating gate.
REFERENCES:
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patent: 4945068 (1990-07-01), Sugaya
patent: 5063171 (1991-11-01), Gill
patent: 5330920 (1994-07-01), Soleimani
patent: 5962914 (1999-10-01), Gardner et al.
patent: 5963839 (1999-10-01), Huang
Kawata Masato
Tashiro Tsutomu
Le Vu A.
NEC Corporation
Smith Bradley
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