Formation of confined halo regions in field effect transistor

Details Formation of confined halo regions in field effect transistor Formation of confined halo regions in field effect transistor

2001-02-12

2001-10-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06297117

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with highly confined halo regions formed by etching away dummy spacers to implant halo dopant through dummy spacer openings that are disposed substantially over drain and source extension junctions.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate structure
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate structure
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate structure
118
and the gate dielectric
116
and between the spacer
122
and the semiconductor substrate
102
.
As the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIG. 2
, to prevent short channel effects as the dimensions of the MOSFET
100
are further scaled down, halo regions
132
and
134
are formed to be beneath the drain extension junction
104
and the source extension junction
106
in the semiconductor substrate
102
. A drain halo region
132
is formed to be beneath the drain extension junction
104
, and a source halo region
134
is formed to be beneath the source extension junction
106
.
The halo regions
132
and
134
are implanted with a halo dopant that is opposite in type to the dopant within the drain and source extension junctions
104
and
106
. For example, when the drain and source extension junctions
104
and
106
are implanted with an N-type dopant for an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions
132
and
134
are implanted with a P-type dopant for preventing short channel effects of the NMOSFET. On the other hand, when the drain and source extension junctions
104
and
106
are implanted with a P-type dopant for a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions
132
and
134
are implanted with an N-type dopant for preventing short channel effects of the PMOSFET. Such halo regions
132
and
134
are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIG. 2
, the halo dopant within the halo regions
132
and
134
diffuse due to transient enhanced diffusion during any integrated circuit fabrication process that heats up the semiconductor substrate
102
. In that case, the drain halo region
132
extends into the drain contact junction
108
, and the source halo region
134
extends into the source contact junction
112
, to undesirably increase the series resistance of the drain and source contact junctions
108
and
112
. In addition, the drain and source halo regions
132
and
134
extend toward the channel region
136
of the MOSFET
100
between the drain and source extension junctions
104
and
106
, to undesirably increase the short channel effects of the MOSFET
100
. Furthermore, the drain and source halo regions
132
and
134
may also extend vertically along the semiconductor substrate
102
from transient enhanced diffusion, undesirably occupying greater volume of the semiconductor substrate
102
.
Nevertheless, halo regions are desired for reducing short channel effects of a MOSFET as the dimensions of the MOSFET are further scaled down. Thus, a mechanism is desired for forming halo regions to be confined to be substantially only beneath the drain and source extension junctions with minimization of transient enhanced diffusion of the halo dopant.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, highly confined halo regions of a MOSFET are formed by etching away dummy spacers to implant halo dopant through dummy spacer openings that are disposed substantially over drain and source extension junctions.
In one embodiment of the present invention, halo regions are formed for a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate. A first dummy spacer is formed on a first sidewall of the gate structure and the gate dielectric, and the first dummy spacer is disposed substantially over a drain extension junction of the field effect transistor. Similarly, a second dummy spacer is formed on a second sidewall of the gate structure and the gate dielectric, and the second dummy spacer is disposed substantially over a source extension junction of the field effect transistor. An insulating material is deposited to cover the first dummy spacer, the second dummy spacer, and the gate structure. The insulating material is polished down until top surfaces of the gate structure, the first dummy spacer, and the second dummy spacer are exposed such that the top surfaces of the gate structure, the first dummy spacer, and the second dummy spacer are level with a top surface of the insulating material.
The first dummy spacer is etched away to form a first spacer opening, and the second dummy spacer is etched away to form a second spacer opening. A halo dopant is implanted through the first spacer opening to form a drain halo region substantially beneath the drain extension junction within the semiconductor substrate and through the second spacer opening to form a source halo region substantially beneath the source extension junction within the semiconductor substrate. The drain halo region and the source halo region are heated up in a thermal anneal process to activate th

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