Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-01-29
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S306000, C438S307000
Reexamination Certificate
active
06303446
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to metal oxide semiconductor (MOS) transistors, particularly to the fabrication of lightly-doped-drain structure of MOS transistors, and more particularly to a process for producing self-aligned lightly-doped-drain structures using pulsed laser energy, thereby simplifying the fabrication of silicon integrated circuits.
As lateral dimensions in silicon integrated circuits decrease, the electronic behavior of the devices which comprise the circuit can be altered substantially. This is the case for a class of devices known as metal oxide semiconductor (MOS) transistors, that are widely used in today's industry. One of the primary problems in designing small MOS devices (those with the gate dimension less than
1
micrometer) is elimination of the hot carrier effect. In these short-channel devices, the electrons which traverse the channel become so energized that they tunnel into the oxide separating the crystalline silicon channel from the gate material. This phenomenon represents an important reliability problem for long term operation. The accepted method to reduce this effect is to grade the doping profile in the source/drain regions of the device from lightly-doped at the gate edge, to more heavily doped where electrical contact is made to the drain region. This reduces the electrical field at the drain of the transistor so that electrons cannot achieve high enough energies to be injected into the oxide.
Typically, formation of this graded profile is carried out in a two step process. In the first step, dopants are ion implanted with the gate structure in place. A light-dose implant is used so that the concentration is low. Next, an oxide layer is deposited in a conformal fashion over the entire structure. The oxide is then etched in an anisotropic manner, leaving a small oxide space at the edge of the gate. Another implant follows the etch step to introduce a large amount of dopants into the region where the device will be contacted by the metal interconnect.
The present invention simplifies this fabrication process by the use of pulsed laser energy in the dopant operation, thereby eliminating the intermediate oxide deposition and etch steps. As a result, the process of the present invention forms the graded doping profile for the source/drain in one step, with the distance between the heavily-doped and lightly-doped regions determined by the laser energy differential used to incorporate the dopants. The process of the present invention results in self-aligned lightly-doped-drains for short-channel MOS transistors, and reduces the number of processing steps, thus simplifying the manufacture of silicon integrated circuits which incorporate MOS transistors.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide self-aligned lightly-doped-drain structures in MOS transistors.
A further object of the invention is to provide a process which simplifies the manufacture of silicon integrated circuits which incorporate MOS transistors.
A further object of the invention is to provide a self-aligned lightly-doped-drain structure for short-channel MOS transistors.
Another object of the invention is to provide an improved process for the formation of a graded doping profile in the source/drain regions of MOS transistors utilizing pulsed laser energy.
Another object of the invention is to provide a process for producing a graded doping profile for the source/drain regions which eliminates the conventional oxide deposition and etch steps.
Another object of the invention is to provide an improved method for fabricating self-aligned lightly-doped-drains for short-channel MOS transistors which involves a single high energy laser pulse for forming the lightly-doped-drain region, followed by a number of low energy laser pulses to heavily dope the source/drain silicon only in a very shallow region.
Other objects and advantages of the invention will become apparent from the following description and accompanying drawing. The present invention involves an improved process for fabricating lightly-doped-drains for short-channel MOS transistors, and results in a graded doping profile in the source/drain regions of the device using pulsed laser energy which eliminates the prior oxide deposition and etch step. In the present invention the graded doping profile for the source/drain is formed in one step, with the distance between the heavily-doped and lightly-doped regions being determined by the laser energy differential used to incorporate the dopants. By use of a single high energy laser pulse to melt the silicon to a significant depth, the amount of dopant incorporated into the silicon is small and diffuse to the edge of the gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse, thus producing self-aligned lightly-doped-drain structures. The process of this invention can be used to simplify the manufacture of silicon integrated circuits which incorporate MOS transistors, thereby reducing costs or increasing profits.
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Carey Paul G.
Weiner Kurt H.
Carnahan L. E.
Gurley Lynne A.
Niebling John F.
The Regents of the University of California
Thompson Alan H.
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