Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-24
2001-11-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S589000
Reexamination Certificate
active
06319777
ABSTRACT:
This invention relates to methods of manufacturing semiconductor devices that have an electrode in an insulated trench, for example as a trench-gate of a power MOSFET or other field-effect device. The invention relates particularly to process steps for lining the trench walls with a lower insulating layer in a lower part of the trench and with a thicker upper insulating layer in an upper part of the trench.
Published PCT patent application WO 99/43029 describes a trench-gate MOS transistor having a lower insulating layer lining a lower part of the trench and a thicker upper insulating layer lining an upper part of the trench. Source-drain regions are present adjacent to the thicker upper insulating layer. Embodiments of the transistor are disclosed that are suitable for EEPROM devices. In an EEPROM embodiment, the trench-gate extends into (but not through) a channel-accommodating region, and the source and drain regions are located at the same surface of the body, but at opposite sides of the trench-gate. The whole contents of WO 99/43029 are hereby incorporated herein as reference material.
WO 99/43029 describes and claims a process for forming the insulated trench by process steps that include:
etching a wide but shallow trench into the semiconductor body from one surface of the body,
filling the wide shallow trench with insulating material for forming the upper insulating layer on the trench walls,
etching a narrow but deep trench into the semiconductor body through the insulating filling of the wide shallow trench,
forming the lower insulating layer on the etched surfaces of the narrow deep trench below the wide shallow trench.
This process requires a photolithographic alignment of a mask defining the narrow deep trench in relation to the wide shallow trench. A lateral displacement error in this alignment renders the upper insulating layer thicker on one side of the trench than on the other side.
It is an aim of the present invention to provide an alternative adaptable process in which the definition of a thicker upper insulating layer in an upper part of the trench can be self-aligned with a lower insulating layer in a lower part of the trench.
According to the present invention, the insulated trench is formed by process steps that include:
(a) etching the trench into a semiconductor body from one surface of the body,
(b) providing the lower insulating layer on the trench walls,
(c) depositing on the lower insulating layer a further layer of a different material from that of the lower insulating layer,
(d) depositing on the further layer a filler material that is of a different material from the further layer,
(e) etching away the further layer from the upper part of the trench walls while using the filler material as an etchant mask, so as to form a space adjacent to the upper part of the trench walls while leaving the further layer in the lower part of the trench,
and (f) providing the thicker upper insulating layer in the space adjacent to the upper part of the trench walls.
Such a process approach not only permits the desired self-alignment but also is readily implemented in a variety of electrode and insulator technologies suitable for use in a wide variety of devices. Several particularly advantageous features and options available with the invention are set out in the appended Claims.
Thus, for example, the filler material and the further layer of different material may be selectively etchable with respect to each other, and one or other may be oxidation-resistant, and/or an electrode material of the device, and/or an insulating material of the device. The filler material may be used in both the lower and upper parts of the trench, or in just one part of the trench.
The filler material and/or the further layer may be retained in the manufactured device or removed.
The bottom of the trench may be free of the lower insulating layer, so that the electrode may contact a region of the body at the bottom of the trench. Thus, the trench may provide an insulated via for the electrode from the surface of the body to a buried region of the body. In the case of a discrete device or integrated circuit comprising a transistor, this electrode may be, for example, a collector connection or a drain connection.
The invention is particularly useful for providing compact insulated trench-gate structures in field-effect devices. Thus, the trench may be etched into a channel-accommodating region of the device. The lower insulating layer may be provided on the bottom of the trench as well as on the lower part of its side walls. Source and/or drain regions may be formed in the body adjacent to the thicker upper insulating layer.
This trench-gate field-effect structure may be used for an EEPROM, for example as in WO 99/43029. However, the invention is of particular utility for a power MOSFET comprising a pattern of transistor cells bounded by the trench-gate. It is particularly useful to provide the thicker insulating layer between the transistor drain and the gate. Thus, the field-effect device may be an inverted transistor having drain regions adjacent to the thicker upper insulating layer. The trench may extend through the thickness of the channel-accommodating region to reach an underlying source region adjacent to the lower insulating layer.
REFERENCES:
patent: 5242845 (1993-09-01), Baba et al.
patent: 5753554 (1998-05-01), Park
patent: 5770514 (1998-06-01), Matsuda et al.
patent: 3932621 (1990-04-01), None
patent: 9943029A1 (1999-08-01), None
Hueting Raymond J. E.
Maas Henricus G. R.
Timmering Cornelis E.
Biren Steven R.
Chaudhari Chandra
Koninklijke Philips Electronics , N.V.
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