Multi stage refresh control of a memory device

Details Multi stage refresh control of a memory device Multi stage refresh control of a memory device

2000-08-30

2001-12-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S203000, C365S236000

Reexamination Certificate

active

06327209

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of dynamic random access memory (DRAM) devices and more particularly, to a synchronous DRAM (SDRAM) with a multi stage refresh control.
2. Description of the Related Art
SDRAMs have been developed as a way of increasing speed of DRAM memory devices. SDRAMs offer a significant increase in speed over conventional DRAMs, operating at speeds above 66 MHz, 100 MHz or faster. DRAMS and SDRAMs are “dynamic” in the sense that the stored data, typically in the form of charged and discharged capacitors contained in memory cells arranged in a large array, will dissipate the charge after a relatively short period of time because of a charge's natural tendency to distribute itself into a lower energy state. Thus, to maintain data integrity, it is necessary to refresh each of the memory rows within a refresh period of time. A refresh operation generally comprises copying the data held in the memory cells into one or more registers or latches and then copying the data in the registers or latches back into the memory cells. In other words, the charged or discharged state of the capacitor must be reapplied to each individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the capacitors used in the memory cell array.
An SDRAM operates in synchronism with a clock signal supplied thereto from a microprocessor, a microcomputer or a memory controller (collectively called a “memory controller”). The memory controller also supplies the SDRAM with a data-read command or a data-write command. In response thereto, the memory device operates to read or write data from or into a selected memory cell or cells in synchronism with the clock signal. These memory cell arrays are typically arranged in rows and columns such that a particular memory cell may be addressed by specifying its row and column within the array. A wordline supplies a gate voltage to access transistors which turn on to connect the capacitors in a row of cells to a set of bit lines and associated sense amplifiers which detect the data stored in the capacitors. In a read operation, an addressed subset of the stored data is sensed by the sense amplifiers and output. A refresh operation is similar to a read operation, but no data is output. In a refresh operation, the sensing of the data in the cells by the sense amplifiers simultaneously results in the data being rewritten back to the cells. The data is thus “refreshed.”
In recent years, the memory capacity, i.e. the number and density of memory cells, of memory devices has been increasing. Accordingly, the size of each cell, including storage capacitor size, has been shrinking which also shortens the cell's data holding time. Typically, a memory device receives the refresh request command in the conventional standardized cycle which is about every 15.625 &mgr;sec. However, with increasing cell number and density, it is becoming more and more difficult to refresh all memory cells at least once within the refresh time period. Hence, what is needed is a memory device with an optimized, controlled refresh operation.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory device, for example, a DRAM or SDRAM wherein all the memory cells are refreshed in response to a refresh command such that a first refresh operation is performed in which a first wordline is first selected and the memory cells associated with the first wordline are refreshed and a second refresh operation is performed in which a second wordline, different from the first, is subsequently selected and the memory cells associated with the second wordline are refreshed. Refresh operations are performed back to back, with the initiation of first and second refresh operations being separated by a period of time such that the current draw from the first refresh operation is about completed prior to the start of the second refresh operation. Hence, at least two wordlines are separately selected and the memory cells associated with each of the at least two wordlines are refreshed each time a refresh command is issued.


REFERENCES:
patent: 5511033 (1996-04-01), Jung
patent: 5566119 (1996-10-01), Matano
patent: 5627791 (1997-05-01), Wright et al.
patent: 5715206 (1998-02-01), Lee et al.
patent: 5901101 (1999-05-01), Suzuki et al.
patent: 6137743 (2000-10-01), Kim
patent: 6144617 (2000-11-01), Takai

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