Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-13
2001-12-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S424000
Reexamination Certificate
active
06333232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation structure in the main surface of a semiconductor substrate and a method of manufacturing the same, and more particularly, it relates to a semiconductor device whose element isolation structure is an STI structure having a bird's beak on its upper end and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor device structured as an integrated circuit, a number of semiconductor elements are formed in active regions of a semiconductor substrate. An element isolation structure electrically isolates these semiconductor elements from each other, for preventing unnecessary interference thereamong. At the same time, in order to implement prescribed functions for which the integrated circuit is designed, an electrical conductor (wire) formed on the element isolation structure selectively connects these semiconductor elements with each other.
When element isolation is incomplete, a leakage current flows between the semiconductor elements. When still another semiconductor element recognizes the leakage current as a signal, it follows that the integrated circuit malfunctions. Therefore, element isolation must be completely performed in order to keep operations of the integrated circuit normal, and hence it can be said that element isolation is an important technique.
In a semiconductor device of such a generation that the minimum line width on a silicon substrate is set to not more than 0.2 &mgr;m, its element isolation structure changes from a conventional LOCOS (local oxidation of silicon) structure to an STI (shallow trench isolation) structure. The conventional element isolation structure formed by a LOCOS method has such disadvantages that (1) a large bird's beak remarkably corrodes and narrows active regions, (2) a channel stop impurity layer formed in a substrate region located under the LOCOS structure is re-distributed in a later heat treatment step, (3) the thickness of a LOCOS oxide film changes between a narrow pitch (width of the element isolation structure or the active regions) and a wide pitch, and (4) a lithography process becomes difficult due to large steps between the active regions and the element isolation structure.
Element isolation by the STI structure has been proposed as a method of solving these problems. Steps of forming the same are briefly described. First, a trench of about 0.1 to 0.5 &mgr;m in depth is formed on the main surface of a silicon substrate by anisotropic etching, and thereafter filled with an insulator. This insulator is flattened by CMP (chemical mechanical polishing) or the like, thereby completing an STI element isolation structure. Since such flattening is performed, the step between the main surface of the semiconductor substrate and the surface of the element isolation structure is smaller as compared with that in an element isolation structure formed by the LOCOS method.
The STI element isolation structure is formed in an initial stage among a series of steps for forming an integrated circuit. In other words, the STI element isolation structure is formed in a step before source and drain regions of a MOS (metal oxide semiconductor) transistor are formed by ion implantation in the vicinity of surfaces of active regions holding the element isolation structure. The STI element isolation structure suppresses such a disadvantage that a channel of a parasitic MOSFET (MOS field-effect transistor) is formed in a field region (region of the element isolation structure: element isolation region) between the active regions. Consequently, an integrated circuit having a small leakage current between active regions holding an element isolation structure is implemented regardless of presence/absence of operations of a MOSFET.
The STI structure is an element isolation structure essentially free from a bird's beak, i.e., involving no bird's beak. In the STI structure free from a bird's beak, however, stress resulting from the shape of a trench forming the STI structure concentrates to a corner part (part between the bottom and the side wall) on the bottom of the trench or the upper end (i.e., opening end) of the trench, to result in formation of a defect in a silicon substrate. When a defect is formed around the trench, a leakage current is increased when the MOSFET is turned off, to remarkably increase power consumption of the semiconductor device.
It is known as a conventional technique that the inner wall of the trench is oxidized thereby the shape of the corner part on the bottom of the trench is rounded while simultaneously a small bird's beak is formed on the upper end of the trench thereby the shape of the trench is rounded so that the stress is relaxed. In this technique, however, it follows that a small bird's beak is formed from the element isolation structure toward the active regions despite the STI structure.
A series of steps of forming an STI structure including a step of forming a bird's beak are now described in detail.
FIGS. 48
to
58
are step diagrams showing a conventional method of forming an STI structure. In order to form the STI structure, a silicon dioxide film
102
, a polysilicon film
103
and a silicon nitride film
104
are formed in this order on a silicon substrate
101
, as shown in FIG.
48
. The silicon dioxide film
102
is also referred to as an underlayer oxide film.
The step shown in
FIG. 49
is then carried out. In the step shown in
FIG. 49
, resist is applied onto the silicon nitride film
104
and thereafter patterned through a transfer step, for forming a resist mask
105
. Thereafter the resist mask
105
is employed as a mask (screen) for executing anisotropic etching, thereby selectively removing the silicon nitride film
104
. Since the ratio of the etching rates for the silicon nitride film
104
and the polysilicon film
103
is sufficiently large, the anisotropic etching stops on the upper surface of the polysilicon film
103
. In this step, the resist mask
105
is also partially removed by the etching. If the quantity of this overetching is large, the resist mask
105
may be entirely removed.
In the subsequent step shown in
FIG. 50
, the resist mask
105
is removed and thereafter anisotropic etching is executed through the patterned silicon nitride film
104
employed as a hard mask, thereby selectively removing the polysilicon film
103
, the silicon dioxide film
102
and the silicon substrate
101
in this order. Needless to say, etchants employed for the anisotropic etching are properly changed following stepwise change of the films to be removed in this step. Through this step, a trench
106
of about 300 nm in depth, for example, is formed in the silicon substrate
101
. In the anisotropic etching performed on the silicon substrate
101
, the etching rate for polysilicon is larger than that for single-crystalline silicon. Therefore, the inner wall of the polysilicon film
103
slightly retreats through the step shown in FIG.
50
.
Then, as shown in
FIG. 51
, an inner wall silicon dioxide film
107
of about 50 nm in thickness is formed on the inner wall of the trench
106
by thermal oxidation. This treatment is referred to as inner wall oxidation. The inner wall oxidation is performed in order to round the shape of a corner part on the bottom of the trench
106
or that of the upper end of the trench
106
for attaining an effect of relaxing stress, as described above. In addition to this effect, an effect of introducing an etching damage layer formed on the surface part of the inner wall of the trench
106
by the anisotropic etching into the inner wall silicon dioxide film
107
for reducing defects (point defects, dislocations etc.) in the silicon substrate
101
and an effect of reducing interface state density between the STI structure and the silicon substrate
101
are also attained by performing the inner wall oxidation.
In the step shown in
FIG. 51
, the inner wall
Jones Josetta
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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