Method of fabricating a field effect transistor with...

Details Method of fabricating a field effect transistor with... Method of fabricating a field effect transistor with...

2000-06-26

2001-12-04

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S303000, C438S305000

Reexamination Certificate

active

06326273

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with a gate dielectric and/or a gate electrode with a trapezoidal shape for maximizing charge accumulation under the gate dielectric of the field effect transistor.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
Conventionally, the gate dielectric
116
for the MOSFET
100
is typically comprised of silicon dioxide (SiO
2
), and the gate electrode
118
is typically comprised of polysilicon. In addition, in the prior art, the gate dielectric
116
and the gate electrode
118
of the MOSFET
100
typically has a rectangular shape in the cross sectional view of FIG.
1
.
As the channel length and width dimensions of the MOSFET
100
are scaled down for enhanced speed performance, the thicknesses of the gate dielectric
116
and the gate electrode
118
are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the MOSFET
100
are scaled down to tens of nanometers, the thickness of the gate dielectric
116
is also scaled down to tens of angstroms when the gate dielectric
116
is comprised of silicon dioxide (SiO
2
). With such a thin gate dielectric
116
, charge carriers easily tunnel through the gate dielectric
116
, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric
116
, gate leakage current undesirably increases resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric
116
, decreased charge carrier accumulation in the channel of the MOSFET may result in undesirable increase in resistance through the channel of the MOSFET. Furthermore, with the thin gate dielectric
116
, the charge accumulation at the gate electrode
118
causes an undesirable increase in charge carrier scattering at the surface of the channel of the MOSFET
100
. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET.
In light of these disadvantages of the thin gate dielectric
116
in the prior art, fabrication of a new gate structure having a gate dielectric with higher thickness is desired for a field effect transistor having scaled down dimensions of tens of nanometers.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a gate structure of a field effect transistor is fabricated with a gate dielectric having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) (i.e., a high dielectric constant material). A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric is comprised of a high dielectric constant material, the gate dielectric has a higher thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO
2
) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
In addition, the gate dielectric and/or the gate electrode of the gate structure of an aspect of the present invention is formed to have a trapezoidal shape for maximizing charge carrier accumulation in the channel of the MOSFET for enhanced speed performance of the MOSFET.
In one embodiment of the present invention, a gate structure for a field effect transistor is fabricated on a semiconductor substrate. A blocking layer is deposited on a top surface of the semiconductor substrate, and a vertical opening is etched in the blocking layer. The vertical opening has at least one sidewall of the blocking layer and has a bottom wall of the top surface of the semiconductor substrate. A respective spacer is formed on each of the at least one sidewall of the vertical opening. The respective spacer is substantially triangular in shape such that the respective spacer has a gradually smaller width toward the top of the vertical opening from the bottom of the vertical opening to form a trapezoidal opening having at least one sidewall of the respective spacer and a bottom wall of the top surface of the semiconductor substrate. The trapezoidal opening is filled with a dielectric material that contacts the top surface of the semiconductor substrate at the bottom wall of the trapezoidal opening. The dielectric material at a top portion of the trapezoidal opening is etched with the dielectric material remaining at a bottom portion of the trapezoidal opening to form a gate dielectric of the field effect transistor. The gate dielectric has a trapezoidal shape with a larger width toward the top from the bottom of the gate dielectric, and the bottom of the gate dielectric contacts the top surface of the semiconductor substrate.
The present invention may be used to particular advantage when the gate dielectric is comprised of a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
), such as aluminum oxide (Al
2
O
3
), titanium dioxide (TiO
2
), or tantalum oxide (Ta
2
O
5
). The gate dielectric has a higher thickness when the gate dielectric is comprised of the high dielectric constant material.
With higher thickness of the g

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