Silicide formation using two metalizations

Details Silicide formation using two metalizations Silicide formation using two metalizations

1998-07-20

2000-05-16

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438366, 438533, 438542, 438595, 438630, 438652, 438656, 438682, 438231, H01L 21336

Patent

active

060636815

ABSTRACT:
Semiconductor device and method for fabricating the same, is disclosed, in which LDD regions and source/drain regions are provided with a silicide for reducing resistances to prevent short channel, the device including a gate insulating film and a gate electrode formed stacked on a prescribed region of a semiconductor substrate, sidewall spacers formed at both sides of the gate insulating film and the gate electrode, first impurity regions formed in surfaces of the semiconductor substrate under the sidewall spacers, second impurity regions formed in the semiconductor substrate on both sides of the sidewall spacers and the first impurity regions, first silicide films at surfaces of the first impurity regions, and second silicide films at surfaces of the gate electrode and the second impurity regions.

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T. Yoshitomi, et al, "Silicided Silicon-Sidewall Source and Drain (S D) Structure for High-Performance 75-nm Gate Length pMOSFETs," 1995 Symposium on VLSI Technology, pp. 11-12.

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