Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-24
2001-12-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S262000, C438S264000, C438S265000, C438S594000, C438S593000
Reexamination Certificate
active
06333228
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of improving the control of bird's beak profile of poly in split gate flash, which in turn improves the erase speed in split-gate flash cell.
(2) Description of the Related Art
The erase performance of a split gate flash memory is primarily governed by the sharpness of the poly tip and the thickness of the inter-poly oxide between the poly tip and the control gate. As is known in the art, the poly tip is formed at the time when the poly-oxide “cap” over the floating poly-gate of the memory cell is formed. The sharper and shorter the poly-tip, the faster is the erase speed of the cell. In other words, the geometry of the poly-tip determines the speed at which electron charge is transferred between the floating gate and the control gate of a split gate flash. In the current manufacturing line, the geometry can be controlled by various techniques, including a method where the different characteristics of polysilicon can be employed to advantage, as disclosed later in the embodiments of the present invention.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure. The forming of a split gate flash cell is shown in
FIGS. 1
a
-
1
f.
In
FIG. 1
a,
layer of gate oxide (
20
) is thermally grown over substrate (
10
) using conventional methods. Next, a first polysilicon layer (
30
) is formed followed by the deposition of nitride layer (
40
). A photoresist layer (
50
) is then formed over the substrate and then patterned with a floating gate pattern, which in turn, is etched into the nitride layer as shown in
FIG. 1
b.
The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon layer that is exposed in the pattern openings in the nitride layer is oxidized to form poly-oxide (
35
) as shown in
FIG. 1
c.
Subsequently, the nitride layer is removed leaving the poly-oxide as shown in
FIG. 1
d,
where now the poly-oxide serves as a hard mask to remove all the first polysilicon portions except those that are covered by the poly-oxide. As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (
37
) is usually not too well controlled. The edge is sometimes rounded off, as seen in
FIG. 1
e,
which is not desirable for achieving fast program erase speed. Sometimes, the edge can break also. It will be shown later in the embodiments of this invention that by employing a different process step, the sharpness of corner edge (
37
) can be preserved such that charge transfer (
23
) between substrate (
10
) and floating gate (
30
), and then the charge transfer (
630
) between the floating gate and control gate, (
70
), is fast. The control gate is formed by depositing a second polysilicon layer over intergate layer (
60
), also known as inter-poly, which separates the two polysilicon layers, namely, the floating poly-gate and the control poly-gate.
Several different methods of forming a split-gate flash memory cell are described in prior art. In U.S. Pat. No. 5,950,087, Hsieh, et al., provide a method for forming a split-gate flash memory cell with reduced size. This is accomplished by forming a self-aligned source line which reduces the number of surface contacts and also by preventing field oxide encroachment into the cell area. In another U.S. Pat. No. 5,970,371, Hsieh, et al., provide a method for forming a split-gate flash memory cell having a sharp beak of poly. The sharp beak is formed through an extra wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. In still another US Patent Hsieh, et al., disclose a method for fabricating a self-aligned edge implanted split-gate flash memory cell to reduce leakage current and improve program speed. This is accomplished by forming a floating gate having thin portions and thick portions where the thin portions overly twice doped regions, thereby reducing the surface leakage current. In yet another U.S. Patent, Hsieh, et al disclose a method for forming a short and sharp gate bird's beak. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form poly-oxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the poly-oxide assumes a sharper shape with smaller size than that is normally found. This results in an increase in the erase speed of the memory cell.
The present invention discloses a method of controlling the integrity of the bird's beak in the first place, thereby assuring the integrity of the resulting poly-tip which in turn yields faster performance for the split-gate flash memory cell.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a method for controlling bird's beak profile of polysilicon in a floating gate in order to improve the erase speed of a split-gate flash memory cell.
It is another object of this invention to provide a method of forming a sharp poly tip in order to improve the erase speed of a split-gate flash memory cell.
It is still another object of this invention to provide a method of forming a thin inter-poly oxide between the floating gate and the control gate in order to improve the erase speed of a split-gate flash memory cell.
It is yet another object of the present invention to provide a method of annealing the polysilicon or the amorphous silicon of the floating gate of a cell in order to improve the erase speed of a split-gate flash memory cell.
These objects are accomplished providing a silicon substrate having a plurality of active and field regions defined; forming a floating gate oxide layer over said substrate; forming a first polycrystalline silicon layer over said floating gate oxide layer; performing a high temperature anneal of said first polycrystalline silicon layer to recrystallize the silicon to form a smooth surface with small grain size; patterning and forming a poly-oxide cap with a well-defined bird's beak over said polycrystalline silicon layer having said smooth surface with said small grain size; using said poly-oxide cap with a well-defined bird's beak as a hard mask, etching said first polycrystalline silicon layer to form a floating gate with a sharp poly-tip underlying said bird's beak; forming a thin inter-poly oxide layer over said poly-oxide cap including said polycrystalline silicon with small grain size; and depositing a second polysilicon layer over said thin inter-poly oxide layer to form a control gate of said split-gate flash memory cell.
The objects are further accomplished by providing a silicon substrate having a plurality of active and field regions defined; forming a floating gate oxide layer over said substrate; forming an amorphous silicon layer over said floating gate oxide layer; performing a high temperature anneal of said amorphous silicon layer to recrystallize the silicon to form a smooth recrystallized silicon layer with small grain size; patterning and forming a poly-oxide cap with a well-defined bird's beak over said recrystallized silicon layer having said smooth surface with said small grain size; using said poly-oxide cap with a well-defined bird's beak as a hard mask, etching said recrystallized silicon layer to form a floating gate with a sharp poly-tip underlying said bird's beak; forming a thin inter-poly oxide layer over said poly-oxide cap including said recrystallized silicon layer with small grain size; and depositing a second polysilicon layer over said thin inter-poly oxide layer to form a control gate of said split-gate flash memory cell.
REFERENCES:
patent: 5858840 (1999-01-01), Hsieh et
Chu Wen-Ting
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Ackerman Stephen B.
Oktay Sevgin
Saile George O.
Smith Matthew
Taiwan Semiconductor Manufacturing Company
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