Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2001-12-11
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S183000, C438S621000, C438S643000
Reexamination Certificate
active
06329232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device by which a gate electrode and a bit line, and a plug of a charge store electrode are simultaneously formed, thus preventing two electrodes from being short.
2. Description of the Prior Art
As the integration level of the semiconductor device becomes higher, the line width of the pattern has become more narrowed. Thus, after the gate electrode is formed, a spacer is formed at the side wall of the gate electrode, so that the bit line and the charge store electrode to be formed later are not short. Then, as the line width of the circuit becomes narrowed, the size of the spacer is reduced accordingly. Due to this, the spacers at the side wall of the neighboring gate electrodes can be short each other. Also it will cause a lot of problems when a subsequent insulating film is formed and then etched to form a contact hole, and the contact hole is buried to form a bit line or a charge store electrode. Thus, the conventional method will degrade reliability of the device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device which can solve the above problem by forming the gate electrode and the bit line, and the plug of the charge store electrode at the time.
A method of manufacturing a semiconductor device according to the present invention is characterized in that it comprises the step of forming a gate pattern in which a spacer is formed on a given region of a semiconductor substrate; forming a junction region on the semiconductor substrate by impurity ion injection process; forming a first insulating film on the entire structure, and then polishing the first insulating film until the upper portion of the gate pattern is exposed, to flatten it; removing the gate pattern to expose the semiconductor substrate, and then forming a gate oxide film on the exposed semiconductor substrate; etching a given region of the first insulating film to form a contact hole exposing the junction region; sequentially forming a barrier layer, a buffer layer and a conductive layer on the entire structure; polishing the conductive layer, the buffer layer and the barrier layer to form a gate electrode and a plug for a bit line and a plug for a charge storage electrode; and forming a second insulating film on the entire structure.
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Chung Sang Tae
Yang Kuk Seung
Hyundai Electronics Co. Ltd.
Nguyen Tuan H.
Pennie & Edmonds LLP
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