Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-03
2001-12-11
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000
Reexamination Certificate
active
06329281
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for fabricating a multi-level interconnection for an integrated circuit device, and more specifically, to methods for making a dual damascene contact.
BACKGROUND OF THE INVENTION
As the level of integration for integrated circuits increases, the number of interconnects necessary for linking up devices increases, too. Therefore, designs employing four or more metallic layers are gradually becoming the norm in the fabrication of integrated circuits. When the level of integration is further increased a high production yield and good reliability is difficult to achieve.
Damascene processing is a fabrication technique that involves the creation of interconnect lines by first etching a trench in a planar dielectric layer, and then filling that trench with a conductor. This is the preferred method for fabricating semiconductor devices with copper metal interconnects because copper is not easily patterned using conventional anisotropic etching techniques. Dual damascene is a multilevel interconnection process in which the filling of the trench and the contact or via openings, which form the connections to the previous interconnect level with metal, is done simultaneously.
Several fabrication schemes exist to form dual damascene structures. A common scheme is known as the full-via first method.
FIGS. 1A-1D
are cross-section views showing steps of a conventional full-via first dual damascene fabrication method. As shown in
FIG. 1A
, a semiconductor substrate
100
is provided having semiconductor devices
110
formed therein. A composite dielectric layer is then formed over the semiconductor substrate, wherein the composite dielectric layer comprises a barrier dielectric layer
120
of a first dielectric material, a via dielectric layer
130
of a second dielectric material, an etch stop dielectric layer
140
of a third dielectric material, and a trench dielectric layer
150
of a fourth dielectric material. A first patterned photoresist layer
160
is formed over the composite layer exposing a via opening
170
. Using standard etching techniques, the via opening
170
is transferred through the trench dielectric layer
150
, etch stop dielectric layer
140
, and via dielectric layer
130
exposing the barrier dielectric layer
120
. Next, referring to
FIG. 1B
, the first patterned photoresist layer is removed and a second patterned photoresist layer
180
is formed over the composite layer to define a trench opening
190
.
Then, referring to
FIG. 1C
, the trench opening
190
is transferred through the trench dielectric layer
150
, whereby the etch stop dielectric layer
140
prevents erosion of the via dielectric layer
130
. Turning now to
FIG. 1D
, using the second patterned photoresist layer
180
as a mask, the trench opening
190
is then transferred through the etch stop dielectric layer
140
exposing the via dielectric layer
130
, and the via opening
170
is transferred through the barrier dielectric layer
120
exposing a conductor
110
within the semiconductor substrate
100
. A conductive layer (not shown) can then be formed over the entire structure, filling both the via and trench openings
170
,
190
. Thereafter, a polishing process can be performed to planarize the dual damascene structure.
The full-via first method is problematic because, for example, the initial via is relatively deep, has a high aspect ratio, and typically requires etching through three dielectric layers (e.g., the trench dielectric, etch stop dielectric, and via dielectric). Forming this deep via can be very slow and requires the etch process to have a high degree of profile control and excellent selectivity to the first patterned photoresist layer in order to provide suitable results. As used herein, selectivity is the etch rate of one dielectric material divided by the etch rate of a second dielectric material wherein a high degree of selectivity implies that the first dielectric etches much slower than the second dielectric. If the selectivity between the first patterned photoresist layer and the dielectric layers is not sufficiently high, the etching process will remove the first patterned photoresist layer and begin eroding the trench dielectric before the via is fully formed.
To overcome some of the difficulties associated with the full-via first method, a few of which are discussed above, an alternate scheme commonly referred to as the partial-via first method can be used.
FIGS. 2A-2D
are cross-sectional views illustrating steps of a conventional partial-via first fabrication method wherein the structural layers are substantially the same as those described above in connection with the full-via first method.
As shown in
FIG. 2A
, a first patterned photoresist layer
160
is formed over the trench dielectric layer
150
to define a via opening
170
. Referring to
FIG. 2B
, the via opening
170
is transferred through the trench dielectric layer
150
and the etch stop dielectric layer
140
but, unlike the full-via first method, the via opening
170
is only partially transferred into the via dielectric layer
130
. Turning to
FIG. 2C
, the first patterned photoresist layer is then removed and a second patterned photoresist layer
180
is formed to define a trench opening
190
. Referring to
FIG. 2D
, the via opening
170
is then transferred through the via dielectric layer
130
exposing the barrier dielectric layer
120
while, at the same time, the trench opening
190
is transferred through the trench dielectric layer
150
exposing the etch stop dielectric layer
140
. The dual damascene structure is then completed using substantially the same steps employed in the full-via first method.
The partial-via first method appears to eliminate some of the difficulties in the full-via first method by reducing the depth of the initial via etch, and thus decreasing the required level of selectivity between the first patterned photoresist layer and the dielectric layers. The partial-via first method may also decrease the time required to make the initial via etch. This method, however, may create additional problems. For example, one problem is that, as shown in
FIG. 2C
, after formation of the second patterned photoresist layer
180
, undeveloped photoresist
200
may be left at the bottom of the partially etched via opening
170
. The undeveloped photoresist
200
may form a barrier which prevents the via opening
170
from being completely transferred through the via dielectric layer
130
while the trench opening
190
is being transferred through the trench dielectric layer
150
. The deeper the partial via opening is during the time of the formation of the second patterned photoresist layer, the more likely that undeveloped photoresist will be left in the via.
However, if the depth of the partial via opening is reduced to avoid leaving undeveloped photoresist in the via, then the time required to complete the via during the completion of the trench is increased, often resulting in the trench etch being completed prior to the completion of the via. As a result, the total time to complete the structure is increased, and the etch stop dielectric layer must have a very high degree of selectivity with respect to the via dielectric layer to prevent the trench opening from being transferred into the via dielectric layer.
Another problem with both the full-via first and partial-via first methods occurs during the polishing process after the conductive layer is deposited to fill the trench and via openings. A common process of planarizing the dual damascene structure and removing the excess conductive layer from above the trench dielectric layer is known as chemical/mechanical polishing (CMP). A critical problem with the CMP process, as well as other polishing methods, is that a limited degree of selectivity is obtainable between the conductive layer and the trench dielectric layer. Thus, the CMP process often erodes the upper portion of the trench dielectric layer and the upper portion of the conductive layer in the t
Lytle Steven Alan
Roby Mary Drummond
Vitkavage Daniel Joseph
Agere Systems Guardian Corp.
Alston & Bird LLP
Quach T. N.
LandOfFree
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