Method for sizing PMOS pull-up devices

Details Method for sizing PMOS pull-up devices Method for sizing PMOS pull-up devices

2000-03-08

2001-11-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S199000, C438S202000, C438S203000, C257S288000, C257S369000

Reexamination Certificate

active

06316301

ABSTRACT:

BACKGROUND
1. Field of Invention
This invention relates generally to CMOS logic and specifically to minimizing silicon area of PMOS pull-up devices in static logic.
2. Description of Related Art
CMOS logic devices typically include one or more PMOS pull-up transistors connected between a voltage supply and an output node and one or more NMOS pull-down transistors connected between the output node and ground potential. Since the mobility of electrons is greater than the mobility of holes, an NMOS transistor is able to conduct a greater current than a PMOS transistor of the same size. Consequently, in CMOS logic devices, the PMOS pull-up transistors are typically sized much larger than their corresponding NMOS pull-down transistors so that the charge path formed by the PMOS pull-up transistors and the discharge path formed by the NMOS pull-down transistors have equal drive strengths. Maintaining equal drive strengths for the charge and discharge paths is necessary to achieve equal charging and discharging rates of the output node, which in turn provides balanced logic transitions.
A well-known sizing factor used to maintain equal drive strength between a PMOS pull-up transistor and an NMOS pull-down transistor is Beta (&bgr;), which is equal the mobility of electrons divided by the mobility of holes. This relationship may be expressed as &bgr;≅&mgr;
n
/&mgr;
p
, where &mgr;
n
is the mobility of electrons, and &mgr;
p
is the mobility of holes. Since the effective drive strength of a transistor is proportional to its width W, the width W
p
of a PMOS transistor which provides the same drive strength as an NMOS transistor of width W
n
is given by W
p
=&bgr;W
n
.
FIG. 1
shows a conventional CMOS inverter
10
having a PMOS pull-up transistor
11
connected between a supply voltage V
DD
and an output node
12
, and having an NMOS pull-down transistor
13
connected between the output node
12
and ground potential. The CMOS inverter inverts an input signal provided to the gates of transistors
11
and
13
to generate an output signal B at output node
12
. When signal A is logic low, the PMOS pull-up transistor turns on and charges the output node
12
toward V
DD
, while the NMOS pull-down transistor
13
turns off and isolates output node
12
from ground potential. When signal A is logic high, the NMOS pull-down transistor
13
turns on and discharges output node
12
toward ground potential, while the PMOS pull-up transistor
11
turns off and isolates output node
12
from V
DD
. Since the PMOS transistor
11
is the only pull-up device, the effective drive strength S
p
of the pull-up path is determined by the width W
p
of the pull-up transistor
11
. Similarly, since the NMOS transistor
13
is the only pull-down device, the effective drive strength of the pull-down path is determined by the width W
n
of the pull-down transistor
13
. Thus, to maintain equal drive strengths S
p
and Sn for the respective charge and discharge paths in the CMOS inverter
10
, the width of the PMOS pull-up transistor W
p
should be equal to the width of the NMOS pull-down transistor W
n
times Beta, i.e., W
p
=&bgr;W
n
. For example, if &bgr;=2, the width W
p
of the PMOS pull-up transistor
11
must be twice the width W
n
of the NMOS pull-down transistor
13
to achieve equal drive strengths for the charge and discharge paths.
FIG. 2
shows a conventional NAND gate
20
having two PMOS pull-up transistors
21
and
22
connected in parallel between V
DD
and an output node
23
, and two NMOS pull-down transistors
24
and
25
connected in series between the output node
23
and ground potential. A first input signal A
0
is provided to the respective gates of the transistors
21
and
24
, and a second input signal Al is provided to the respective gates of transistors
22
and
25
. If either of the input signals A
0
or A
1
is logic low, the corresponding PMOS pull-up transistor
21
and/or
22
turns on and charges the output node
23
toward V
DD
, thereby driving the output signal B to logic high. Since only one of the input signals A
0
or A
1
must be logic low to drive output signal B to logic high, sometimes only one of the PMOS pull-up transistors
21
and
22
turns on to charge the output node
23
toward V
DD
. Thus, the effective drive strength S
p
of the charge path is equal to that of one of the PMOS pull-up transistors
21
or
21
, i.e., S
p
≅W
p
.
Both input signals A
0
and A
1
must be logic high in order to discharge the output node
23
toward ground potential through series-connected NMOS pull-down transistors
24
and
25
. Since the resistance of two series-connected transistors is twice that of a single transistor, the effective drive strength of the discharge path through NMOS pull-down transistors
24
and
25
is about one-half the effective drive strength of a single NMOS transistor, i.e., S
n
≅W
n
/2. Thus, in order to maintain equal drive strengths for the charge and discharge paths of the NAND gate
20
, the width of each of the PMOS pull-up transistors
21
and
22
is sized by multiplying the effective NMOS transistor width times Beta, i.e., W
p
=&bgr;W
n
/2.
It is always desirable to reduce the size of a circuit such as, for instance, a CMOS logic device, since any reduction in circuit size typically reduces manufacturing costs and power consumption. Further, reducing the silicon area of a circuit advantageously allows for the circuit to be more easily fabricated using smaller technologies.
While it is desirable to reduce transistor size in order to conserve silicon area, the proper ratio between PMOS and NMOS devices in logic devices must be maintained in order to preserve the balance of the circuit. Otherwise, one input level may overpower the other input level, which in turn could result in erroneous data. Thus, it is desirable to reduce transistor size without sacrificing performance or upsetting the balance of current-carrying capability between PMOS pull-up and NMOS pull-down devices.
SUMMARY
A method is disclosed that allows for a reduction in silicon area in applications where a number of input signals simultaneously transition to the same logic state. In accordance with one embodiment of the present invention, the PMOS pull-up devices of a logic circuit are sized relative to the NMOS pull-down devices therein according to the number of the PMOS pull-up devices that simultaneously turn on. For example, in one embodiment, the PMOS pull-up transistor width is determined by multiplying the NMOS pull-down transistor width by a predetermined factor indicative of a current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors and then dividing by the number of PMOS pull-up transistors that simultaneously turn on to charge the output node high. In one embodiment, the width W
p
of each parallel-connected PMOS pull-up device sized relative to the width W
n
of each series-connected NMOS pull-down device may be expressed as W
p
=W
n
(&bgr;/kN), where &bgr; is the current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors, k is the number of PMOS devices that simultaneously turn on, and N is the number of NMOS devices. In another embodiment, the width W
p
of each series-connected PMOS pull-up device sized relative to the width W
n
of each parallel-connected NMOS pull-down device may be expressed as W
p
=W
n
(&bgr;N/k). By factoring the number of PMOS pull-up devices that simultaneously turn on into sizing of the PMOS pull-up devices, the present invention may reduce silicon area of logic devices having PMOS pull-up transistors and NMOS pull-down transistors.


REFERENCES:
patent: 5880967 (1999-03-01), Jyu et al.
Pham et al. “Simple 6-Bit Neural-based A/D converter using CMOS inverters” 1996 IEEE 0-7803-3073-0/96 p. 357-360.

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