Semiconductor device with salicide structure and fabrication...

Details Semiconductor device with salicide structure and fabrication... Semiconductor device with salicide structure and fabrication...

1999-12-08

2001-10-02

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06297094

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a self-aligned silicide (SALICIDE) structure and a fabrication method thereof and more particularly, to a semiconductor device equipped with nonvolatile memory cells formed by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and a peripheral circuitry including MOSFETs on a semiconductor substrate, in which the MOSFETs of the peripheral circuitry have silicide layer at their source/drain regions while the MOSFETs of the memory cells have no silicide layers at their source/drain regions, and a fabrication method of the semiconductor device.
2. Description of the Prior Art
Conventionally, the miniaturization and integration of semiconductor elements and components have been progressing perpetually in semiconductor integrated circuit devices.
In recent years, highly-integrated semiconductor integrated circuit devices (i.e., LSIs) designed according to the design rule as small as 0.15 to 0.25 &mgr;m, such as memory devices and logic devices, have been fabricated and actually used. These LSIs are often constituted by the use of MOSFETs, because MOSFETs are miniaturized more readily than bipolar transistors.
According to the progressing integration of the semiconductor elements and components in the LSIs, there has been the need to decrease the length of the gate electrodes and the width of the source/drain regions in the MOSFETs. However, the decrease in the length of the gate electrodes and the width of the source/drain regions increases their electric resistance and as a result, there arises a problem that the operation speed of the inner circuits of the LSIs tends to be badly affected.
To solve this problem, refractory silicide layers, which are low in electric resistance, have been widely used for the source/drain regions formed in a single-crystal silicon (Si) substrate and the gate electrodes made of polycrystalline Si (i.e., polysilicon) in the miniaturized MOSFETs. The refractory silicide layers are typically located on the surface areas of the source/drain regions and the gate electrodes.
The silicide layers are typically formed by the use of the well-known SALICIDE technique. Specifically, first, a refractory metal such as a titanium (Ti) film is formed in contact with the single-crystal Si source/drain regions and the polysilicon gate electrodes, Then, the refractory metal film, the source/drain regions, and the gate electrodes are heat-treated to cause a silicidation reaction between the refractory metal and Si. Thus, refractory silicide films are formed at the surface areas of the source/drain regions, and the gate electrodes, respectively. Finally, the unreacted refractory metal film is removed. Since the refractory silicide films are formed in self-alignment to the gate electrodes and an isolation dielectric without any masking film, this formation method is termed the “self-aligned silicide” technique, or the “SILICIDE” technique. Also, the source/drain regions and the gate electrodes equipped with the silicide films thus formed are termed the “SILICIDE” structure.
FIGS. 1A
to
1
K show a conventional fabrication method of a flush nonvolatile semiconductor memory device which is termed a flush Electrically Erasable Programmable Read-Only Memory (EEPROM), in which the SALICIDE technique is used.
This memory device is comprised of a lot of nonvolatile memory cells formed by n-channel MOSFETs with floating gates and a peripheral circuitry formed by n- and p-channel MOSFETs. Therefore, the peripheral circuitry has the Complementary MOS (CMOS) structure. The peripheral circuitry serves to provide control operations for the memory cells, such as the reading operation and the writing or reprogramming operation. The memory cells are arranged in a matrix array in a memory cell area. The n- and p-channel MOSFETs of the peripheral circuitry are arranged in peripheral NMOS and PMOS areas, respectively.
In
FIGS. 1A
to
1
K, however, two adjoining ones of the n-channel MOSFETs in the memory cells, one of the n-channel MOSFETs in the peripheral circuitry, and one of the p=channel MOSFETs in the peripheral circuitry are explained below for the sake of simplification of description.
First, as shown in
FIG. 1A
, an isolation dielectric
102
with a specific depth is selectively formed at the main surface of a p- or n-type single-crystal Si substrate
101
by the well-known Local Oxidation of Silicon (LOCOS) process, thereby defining a peripheral NMOS area
151
and a peripheral PMOS area
152
of the peripheral circuitry and a memory cell area
153
.
Next, a patterned photoresist film
103
a
with a window uncovering the peripheral NMOS area
151
is formed using a photolithography technique. Then, using the photoresist film
103
a
as a mask, boron (B) is selectively ion-implanted into the substrate
101
, thereby forming a p-type well
104
in the peripheral NMOS area
151
, as shown in FIG.
1
B. Thereafter, the photoresist film
103
a
is removed.
In the same way as that of the p-type well
104
, an n-type well
105
is formed in the peripheral PMOS area
152
and a p-type well
106
is formed in the memory cell area
153
, as shown in FIG.
1
C.
A silicon dioxide (SiO
2
) film
137
is formed on the whole main surface of the substrate
101
by a thermal oxidation process, as shown in FIG.
1
D. By successive Chemical Vapor Deposition (CVD) processes, a polysilicon film
13
B (approximately 150 nm in thickness) is formed on the whole SiO
2
film
137
, an ONO film
139
is formed on the whole polysilicon film
138
, and a tungsten polycide film
140
is formed on the whole ONO film
139
. The ONO film
139
is formed by three stacked subfilms, i.e., a SiO
2
subfilm, a silicon nitride (Si
3
N
4
) subfilm, and a SiO
2
subfilm. The tungsten polycide film
140
is a composite film of an impurity-doped polysilicon subfilm and a tungsten silicide subfilm, where the impurity is typically phosphorus (P).
Thereafter, a patterned photoresist film
103
b
with a pattern covering the areas for gate electrodes if formed using a photolithography technique. Then, using the photoresist film
103
b
as a mask, the polysilicon film
138
, the ONO film
139
, and the tungsten polycide film
140
are successively patterned, thereby forming gate electrodes
111
for the n-channel MOSFETs arranged in the memory cell area
153
, as shown in FIG.
1
E. The gate electrodes
111
are formed by the combination of the remaining polysilicon film
138
, the remaining ONO film
139
, and the remaining tungsten polycide film
140
. In this patterning process, the SiO
2
film
137
is not patterned.
A polysilicon film (not shown) is formed on the whole SiO
2
film
137
to cover the whole substrate
101
and then, the polysilicon film is patterned to form gate electrodes
112
for the n- and p-channel MOSFETs in the peripheral NMOS and PMOS regions
151
and
152
. In this patterning process, the SiO
2
film
137
is not patterned.
The SiO
2
film
137
is selectively etched using the gate electrodes
111
and
112
as a mask, thereby forming respective gate oxide films
107
and
108
. The state at this stage is shown in FIG.
1
E.
Following this step, a SiO
2
film (not shown) is formed on the uncovered main surface of the substrate
101
to cover the gate electrodes
111
and
112
by a CVD process. The SiO
2
film is then etched back by an anisotropic etching process, thereby forming sidewall spacers
113
at each side of the gate electrodes
111
and
112
, as shown in FIG.
1
F.
An n-type impurity such as arsenic (As) is selectively ion-implanted into the p-type wells
104
and
106
while covering the peripheral PMOS area
152
by a mask. Thus, the n-type impurity is selectively implanted into the p-type wells
104
and
106
in self-alignment to the gate electrodes
111
and
112
, the sidewall spacers
113
, and the isolation dielectric
102
.
In the same way as the p-type wells
104
and
106
, a p-type impurity such as boron (B) is selectively ion-implanted into the n-t

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