Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-18
2001-11-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S106000, C438S107000, C438S108000, C438S109000, C438S121000, C257S700000, C257S703000, C257S708000, C439S066000, C439S091000, C439S591000
Reexamination Certificate
active
06319829
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit construction and, more particularly, to an enhanced interconnection to ceramic substrates of a semiconductor chip or printed circuit board.
BACKGROUND OF THE INVENTION
The evolution of electrical and electronic circuitry from component circuits to integrated circuits, particularly microelectronic integrated circuits, has presented various new considerations in circuit design. Among these considerations is the necessity of connecting circuits on the semiconductor chip to other chips or devices mounted on a printed circuit board. This is because not all connections can be made inside a single chip. Therefore, it is necessary to connect externally to different I/O areas with external conductors, such as wires. Likewise, power must be supplied to the semiconductor chips.
In order to eliminate use of wiring, chip carriers have found widespread use. The chip carrier consists of a substrate having I/O pads on either side with internal connections between the I/O pads. Referring to
FIG. 1
, an exemplary such prior art integrated circuit is illustrated with a semiconductor chip
10
, a chip carrier
12
, and a printed circuit board
14
. The chip
10
is connected to I/O pads of the chip carrier
12
using, for example, solder balls
16
. Likewise, opposite I/O pads of the chip carrier
12
are connected to the board using solder balls
16
. As is known, interconnections can also be provided by controlled collapsible chip connectors (C
4
s), columns, pins or the like. The solder balls
16
on either side of the chip carrier
12
are formed in an array corresponding to the location of the I/O pads. This construction is conventionally referred to as a ball grid array (BGA). Although not shown, the chip carrier
12
may be modified to include pins brazed to the I/O pads for connection to the board
14
to define a pin grid array (PGA).
With a conventional design, such as illustrated in
FIG. 1
, the chip has a relatively low thermal coefficient of expansion (TCE) on the order of 3 ppm/° C. The chip carrier
12
is typically constructed of a glass ceramic and also has a TCE of about 3 ppm/° C. The board
14
which is typically constructed of an organic material has a substantially higher TCE on the order of about 19 ppm/° C., typically. The difference in thermal expansion, particularly between the carrier
12
and the board
14
, limits reliability due to fatigue from thermal cycling of the interconnections between the chip carrier
12
and the board
14
. The fatigue occurs in thermal on/off cycling due to the thermal expansion mismatch between the carrier
12
and board
14
which are joined, for example, by solder. Depending on construction of the carrier
12
, the chip
10
to carrier
12
interconnects can also be affected by this phenomenon.
The present invention is directed to overcoming one or more of the problems discussed above, in a novel and simple manner.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor chip interposer for increasing fatigue life of interconnections by distributing mismatch of thermal coefficient of expansion between circuit components.
Broadly, there is disclosed herein a semiconductor chip interposer for increasing fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The interposer comprises a thin substrate having a TCE intermediate the relatively high TCE and the relatively low TCE and a plurality of through holes that are electrically insulated from one another. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.
In one embodiment of the invention the substrate is a thin metal plate having a thickness in the range of 2-8 mils. The substrate includes an insulation coating on the thin metal plate including on walls of the through holes. The insulation coating comprises an oxide coating.
In another embodiment of the invention the substrate comprises a ceramic substrate.
There is disclosed in accordance with another aspect of the invention a semiconductor chip interposer including a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE. An insulation coating on the thin metal plate is also included on walls of the through holes. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.
It is a feature of the invention that the thin metal plate is a metal foil having a thickness in the range of 2-8 mils.
It is another feature of the invention that the insulation coating comprises an oxide coating.
It is still a further feature of the invention that the chip comprises a multi-chip module and the interposer comprises a segmented interposer.
It is still another feature of the invention to provide conductive I/O pads on either side of the through openings electrically connected to the conductive material.
It is yet another feature of the invention that the second component is a glass/ceramic substrate having I/O pads and the interposer is joined to the substrate by co-sintering the substrate I/O pads and the interposer I/O pads.
It is still a further feature of the invention to provide conductive pins brazed to I/O pads on one side of the interposer. In one aspect, the second component is a glass/ceramic substrate having I/O pads and the interposer is joined to the substrate by co-sintering using the substrate I/O pads and the interposer I/O pads to provide a glass-ceramic pin grid array.
Further features and advantages of the invention will be readily apparent from the specification and from the drawing.
REFERENCES:
patent: 4074342 (1978-02-01), Honn et al.
patent: 4603023 (1986-07-01), Mack et al.
patent: 4617730 (1986-10-01), Geldermans et al.
patent: 4855871 (1989-08-01), Young
patent: 5073840 (1991-12-01), Coors
patent: 5177594 (1993-01-01), Chance et al.
patent: 5313366 (1994-05-01), Gaudenzi et al.
patent: 5404044 (1995-04-01), Booth et al.
patent: 5473120 (1995-12-01), Ito et al.
patent: 5474458 (1995-12-01), Yafi et al.
patent: 5484647 (1996-01-01), Nakatani et al.
patent: 5504035 (1996-04-01), Rostoker et al.
patent: 5571593 (1996-11-01), Arldt et al.
patent: 5668059 (1997-09-01), Christie et al.
patent: 5866948 (1999-02-01), Murakami et al.
patent: 6050832 (2000-04-01), Lee et al.
Schueller et al, 1997 IEEE/CPMT Electronic Packaging Technology Conference, 219-227.*
IBM Technical Disclosure Bulletin—vol. 37, No. 02A, Feb. 1994; No. 04B, Apr. 1994; No. 10, Oct. 1994; No. 11, Nov. 1994; vol. 36, No. 12, Dec. 1993; vol. 32, No. 3B, Aug. 1989; vol. 24, No. 12, May 1982; vol. 24, No. 6, Nov. 1981.
Pasco Robert W.
Reddy Srinivasa S. N.
Vallabhaneni Rao V.
International Business Machines - Corporation
Lytle Craig P.
Smith Matthew
Wood Phillips VanSanten Clark & Mortimer
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