Method of making self-aligned bit-lines

Details Method of making self-aligned bit-lines Method of making self-aligned bit-lines

2000-07-20

2001-12-11

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S669000, C438S720000, C438S639000

Reexamination Certificate

active

06329255

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method for making a self-aligned bit-line on a substrate.
2. Description of the Prior Art
A dynamic random access memory (DRAM) comprises an enormous amount of memory cells, each of which comprises a metal oxide semiconductor (MOS) and a capacitor. Each MOS and capacitor link with bit-lines through word lines to determine the location of each memory cell.
The design of a capacitor of a memory cell is based on two electric pole layers. The upper layer is a field plate and the lower layer is a storage node. These layers are separated by a cell dielectric layer. When one electric pole layer is subjected to a voltage, an electric charge of the corresponding value is induced in the other electric pole layer. The data storing and retrieving functions are achieved in this way. The lower layer storage node, in the form of a node contact acting as a connecting line, connects electrically with the drain of a MOS to store and retrieve data.
In order to raise the density of DRAM, when making lower layer storage nodes of the DRAM, landing pads are generally used in forming node contacts, which connect the MOS and capacitor with bit-lines. However, with advances in wafer production, the size of dynamic memory cells is being designed smaller and smaller. For this reason, the improvement and control of DRAM production processes has become an important subject in the field.
Please refer to
FIG. 1
to FIG.
4
.
FIGS. 1
to
4
show the fabrication processes of a lower layer storage node
28
of a capacitor according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprises a substrate
12
, a landing pad
16
located on the substrate
12
, a first dielectric layer
14
deposited on the surfaces of the substrate
12
and the landing pad
16
, two bit-lines
18
located on the first dielectric layer
14
for data transmission, and a second dielectric layer
23
deposited over the surfaces of the two bit-lines
18
and the first dielectric layer
14
. The two bit-lines are covered by a metallic silicide layer
20
, which lowers the contact resistance of the surfaces of the bit-lines
18
.
As shown in
FIG. 2
, according to the prior art method for making a node contact hole
26
, the manufacturer forms a photoresist layer
24
on the surface of the second dielectric layer
23
, and uses a lithographic process to pattern the location of the node contact hole
26
by forming a hole
25
in the photoresist layer
24
. Next, the manufacturer performs an etching process, using the photoresist layer
24
as a hard mask, vertically removing the second dielectric layer
23
and then the first dielectric layer
16
along the hole
25
, forming a node contact hole
26
on the landing pad
16
between the two bit-lines
18
.
As shown in
FIG. 3
, after removing the photoresist layer
24
, the manufacturer deposits a doped polysilicon layer over the surface of the substrate
10
, which fills the node contact hole
26
, and, with an etching back process or a chemical mechanical polishing (CMP) process, levels the doped polysilicon layer in the node contact hole
26
with the second dielectric layer
23
, forming a node contact
27
.
And as shown in
FIG. 4
, the manufacturer then evenly deposits an amorphous silicon layer over the surface of the substrate
10
, and with a photolithographic process and an etching process forms a lower layer storage node
28
on the top of the node contact hole
26
. A hemi-spherical grain (HSG) process is performed to increase the surface area of the lower layer storage node
28
.
FIG. 5
shows a misalignment that can occur when making the lower layer storage node
28
of a capacitor according to the prior art. When etching the amorphous silicon layer to make the storage node
28
, if the pattern of the location is not accurately transferred during the photolithographic process, a misalignment occurs. This misalignment allows the doped polysilicon in the node contact hole
26
(the node contact
27
) to be etched off during the etching of the amorphous silicon. This results in a recess
29
, which causes an insufficient thickness of the ONO layer over the doped polysilicon
27
in the recess
29
during later processes when forming a cell dielectric layer of oxide-nitride-oxide (ONO) over the storage node
28
. This, in turn, results in a low-quality product. Additionally, since the node contact
27
is made after the two bit-lines
18
, the line width of the bit-lines
18
must be made very narrow to avoid misalignment during the formation of the node contact hole
26
. Unfortunately, the narrowing of line width results in a high resistance in the bit-lines
18
, which affects the transmission speed, and which may even interrupt data transmission in the bit-lines
18
.
Moreover, as shown in
FIGS. 1
to
4
, the process for making the lower layer storage nodes
28
of the DRAM requires two photolithographic processes to define the location of the node contact hole
26
and the storage node
28
. For this reason, a landing pad has to be made before hand, which increases the DRAM manufacturing cost. Furthermore, with the size of the substrate decreasing, the precision of the photolithographic pattern transfer is lowered, and the subsequent yield rate is thus lowered.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for making a self-aligned bit-line on a substrate. Another objective of the present invention is to eliminate the problem of misalignment that occurs when making storage nodes.
In the preferred embodiment, the surface of a semiconductor substrate has a dielectric layer, which has a plurality of node contact holes and bit-line contact holes. A first conducting layer is first formed over the surface of the substrate, filling each node contact hole and bit-line contact hole. A protection layer is then formed over the first conducting layer, and an etching process then etches the protecting layer and the first conducting layer so as to form each node contact and bit-line contact. Next, a spacer is formed around each node contact, and a second dielectric layer is deposited over the substrate. An etching process etches the second dielectric layer down to the first dielectric layer and down to the surface of each bit-line contact, forming a trench for each bit-line in the second dielectric layer. A second conducting layer is then deposited over the substrate, filling each bit-line trench. In an etching back process, the second conducting layer is removed from the surface of the second dielectric layer, and is partially removed the second conducting layer in the trench down to a certain depth, so as to form each bit-line. A third dielectric layer is deposited over the substrate, filling each bit-line trench, and a planarizing process levels the tops of the second dielectric layer and the third dielectric layer in each trench with the first conducting layer on top of each node contact. Finally, a storage node is made on top of each node contact.
In the present invention, bit-lines are formed based on a difference in height, which is created through the etching process of conducting layers, and the conducting layer left in the lower region assumes the function of a landing pad, so the entire manufacturing process is simplified and costs are reduced.


REFERENCES:
patent: 5907781 (1999-05-01), Chen et al.
patent: 6114202 (2000-09-01), Tseng

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