Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-12
2001-12-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S306000, C438S307000, C438S527000, C438S529000, C438S585000
Reexamination Certificate
active
06326251
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to a method of manufacture and a structure in which a gate conductor is formed to include a metal contact in a scaled device.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate dielectric and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source and drain regions. The gate conductor typically is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs N-type junctions placed into a P-type substrate. Conversely, a typical p-channel MOS transistor comprises P-type junctions placed into an N-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a well exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both N-type and P-type transistors (i.e., Complementary MOS, “CMOS”) are needed.
A common trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source and drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have as small as 0.20 microns critical dimensions. As feature sizes decrease, the sizes of the resulting transistors as well as the interconnections between transistors also decrease. Having smaller transistors allows more transistors to be placed on a single monolithic substrate. Accordingly, relatively large circuits can be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features, in combination, allow for higher speed integrated circuits to be constructed that have greater processing capabilities and that produce less heat.
The benefits of high-density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and xray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive sub threshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor. In view of these considerations, certain scaling limits are being reached.
Additional problems result from reducing the channel length in scaled transistors. Because lithography equipment is limited to a smallest dimension, the channel length cannot be made shorter than the smallest dimension using currently known processing steps. Such channel length limitation has heretofore provided a lower limit on the shortest obtainable channel length.
As engineers strive to design devices having minimal size, there also is a continuing need to increase device performance. In general, it is known that metal contacts provide excellent performance in MOSFET devices. Metal often is not used as a gate conductor in scaled devices, however, because of its tendency to spike through the gate dielectric in scaled devices whenever processing techniques include subjecting the wafer to a temperature in excess of 500 degrees Celsius. Because many processing steps typically include subjecting a wafer to a rapid thermal annealing step wherein the temperature exceeds 500 degrees Celsius, conductive polysilicon is formed adjacent to the device gate's oxide layer to carry electrical charge up to the gate oxide instead of metal.
A metal contact is typically used to contact the polysilicon and is formed only in final fabrication steps in which the metallization layers are formed to interconnect the devices on the substrate. Using the polysilicon layer is advantageous as a gate contact material in that it allows the substrate to be subjected to temperatures in excess of 500 degrees Celsius as is common in most annealing process steps.
Devices using polysilicon gate contacts, however, do not perform as efficiently as do devices having metal gate contacts because metal gate contacts provide greater conductivity as compared to polysilicon gate contacts. Additionally, polysilicon gate contacts tend to suffer from poly depletion and boron penetration effects. Accordingly, there is a need for a scaled MOSFET device having metal gate contacts and a need for a process for forming the same.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the transistor formation process according to -the present invention in which a metal gate conductor is deposited and formed after the source and drain regions, lightly doped regions (LDD), gate insulator layers and salicidation layers are formed on the substrate. More specifically, after each doping step to form source and drain regions and LDD regions in the device channels, an annealing step is performed to repair crystalline lattice damage that may result from the ion implantation. Additionally, an annealing step is performed after a silicide metal is formed on the top surface of the substrate as a part of forming salicides to improve device conductivity. Each of these annealing steps can cause metal gate conductors to spike through the gate insulator stack thereby ruining the device. As a result, polysilicon gate conductors that can withstand the aforementioned annealing steps are typically used.
According to the present invention, however, the benefits of metal gate conductors can be realized by forming a metal gate conductor after all of the annealing steps are complete. In order to form the metal gate conductor at the end of the fabrication process, a first selective layer is formed on top of a gate insulator. A second selective layer relative to the first selective layer is formed about the gate stack after the source and drain regions, the LDD regions and the salicidation layer are formed. Accordingly, the first selective layer may then be removed in a selective etch step to create an aperture above the gate insulator to receive and form the metal gate conductor. Once the metal gate conductor is formed, the remaining steps of forming an integrated circuit may be completed. Additionally, by
Fulford Jr. H. Jim
Gardner Mark I.
Spikes, Jr. Thomas E.
Advanced Micro Devices
Garlick Bruce
Harrison James A.
Lytle Craig P.
Smith Matthew
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