Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-09-05
2001-12-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S626000, C438S629000, C438S645000, C438S652000, C438S672000, C438S675000
Reexamination Certificate
active
06326320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates cover of conductor plug that inside trench, and more particularly relates to a method for providing required cover without disadvantages such as porous structure and wastage of conductor plug.
2. Description of the Prior Art
In contemporary semiconductor devices, trench usually is formed in substrate and is used to form shallow isolation by filling dielectric material into trench. However, in some semiconductor devices, such as power integrated circuits, materials filled into trench comprise conductor. Refers to
FIG. 1A
that briefly illustrates conventional trench structure with conductor plug, wherein conductor plug
11
is located inside trench that is inside substrate
10
and is covered by dielectric plug
12
. Moreover, an optional dielectric plug may exist at bottom part of trench and be located under conductor plug
11
. It should be noted that substrate
10
can further comprise some structures, such as transistors and conductor lines, in and on it.
Conventional method for covering conductor plug
11
by conductor plug comprises following steps: forms a low O3 flow rate tetraethyl-orthosilicate (TEOS) layer on substrate and fills empty part of the trench; then forms a high O3 flow rate flow rate tetraethyl-orthosilicate layer on the low O3 flow rate TEOS layer; and then etch back these TEOS layers until substrate is not covered by these layers but conductor plug still is covered. Herein, low O3 flow rate TEOS layer is used as a buffer layer and high O3 flow rate flow TEOS layer is used to provide a smoother surface. Moreover, deposit rate of these layers is about 1500 angstroms per minutes and the method can further comprises an anneal process before etch back these layers. However, as
FIG. 1B
shows, an unavoidable defect of the method is the porous structure of O
3
/TEOS layer
14
, especially as is treated by an etch back process, the porous surface will induces some disadvantages in following process.
Beside, when conductor plug
11
is a polysilicon plug, another conventional method for forming dielectric plug
12
is that directly oxidates the polysilicon plug to form oxide plug
15
on conductor plug
11
, as shown in FIG.
1
C. Advantages of the method include simply process and smooth surface of dielectric plug (oxide plug). However, unavoidable defects include exhaust of polysilicon plug for part of polysilicon plug is depleted during the oxidation process. Further, because the trench structure is part of a semiconductor device, sometime the depleted polysilicon plug is improper and sometime even dielectric plug can not be oxide plug
15
.
Accordingly, it is obvious that conventional methods for forming dielectric layer on conductor plug of trench structure are defective and then a mendable method is required, especially when importance of power integrated circuits is increased.
SUMMARY OF THE INVENTION
The primary object of the invention is to propose a method that forms oxide layer on conductor plug of trench structure.
Another object of the invention is to modify conventional trench structure that comprises conductor plug, and particularly to improve conventional disadvantages of dielectric layer such as low deposit rate, porous structure and depleted conductor plug.
A further object of the invention is to present a practical and manufacturable method for covering conductor plug of trench structure.
In order to achieve previous objects of the invention, a method comprises following essential steps are present as a preferred embodiment: First, provide a substrate where a trench locates inside the substrate, herein the trench is partly filled by a conductor plug. Second, forms a plasma enhanced tetraethyl-orthosilicate layer on the substrate, herein the plasma enhanced tetraethyl-orthosilicate layer also fills the trench and covers the conductor plug. Finally, removes the plasma enhanced tetraethyl-orthosilicate layer until the substrate is not covered by the plasma enhanced tetraethyl-orthosilicate layer, herein the conductor plug still is covered by the plasma enhanced tetraethyl-orthosilicate layer.
Another embodiment is a method for covering polysilicon plug inside trench by dielectric layer. First, provides a substrate that comprises a trench. Then, forms a polysilicon plug inside the trench. And then, forms a plasma enhanced tetraethyl-orthosilicate layer on the substrate, herein the plasma enhanced tetraethyl-orthosilicate layer also fills the trench and covers the polysilicon plug.
Obviously, main spirit of the invention is to cover the conductor plug by plasma enhanced tetraethyl-orthosilicate layer that structure is compacted and deposit rate is high, and then some disadvantages of well-known technology are overcame.
REFERENCES:
patent: 6159835 (2000-12-01), Visokay et al.
Chu Jason Chien-Song
Su Mike Wen-Jeh
Yang Yi-Chuan
Mosel Vitelic Inc.
Niebling John F.
Zarneke David A
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