Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-03
2001-10-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S298000, C438S307000, C438S454000
Reexamination Certificate
active
06306711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating high-voltage lateral double-diffused metal oxide semiconductor (LDMOS).
2. Description of the Related Art
Due to the increasing number of semiconductor elements incorporated in integrated circuits, the size of metal oxide semiconductor (MOS) components needs to be decreased. Accordingly, as the channel length of the MOS is decreased, the operating speed is increased. However, there is an increased likelihood of a problem, referred to as “short channel effect”, caused by the reduced channel length. If the voltage level is fixed, according to the equation of electrical field =electrical voltage/channel length, as the channel length is shortened, the strength of electrical field is increased. Thus, as the strength of electrical field increases, energy of electron increases and electrical breakdown is likely to occur.
In general, a high voltage is on an order of about 8 vol or above. A MOS that can be operated under high voltage is called a high-voltage MOS. An isolation layer and a drift region below the isolation layer are used to increase the distance between the source/drain and the gate electrode in the high-voltage MOS. Thus, the MOS is able to work normally under the high voltage.
FIG. 1
is a schematic, cross-sectional view of a conventional LDMOS.
In
FIG. 1
, a conventional LDMOS including a P-type silicon substrate
100
, a field oxide layer
101
, a gate oxide layer
102
, a gate layer
103
, a N
+
drain region
104
, an N
−
drift region
105
, an N
+
source region
106
, a P-doped region
107
, and a P
+
-doped region
108
.
In the conventional LDMOS, the drift region
105
is under the crossing wire
109
. While operating the conventional LDMOS under high voltage, high electrical field crowding occurs at the junction
110
between the drift region
105
and the channel. Thus, the breakdown voltage is decreased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provide a method for fabricating a high-voltage LDMOS that decreases the strength of the electrical field at the junction between the drift region and the channel.
In the high-voltage LDMOS of the present invention, a field metal plate or an electrical field shield conductive layer, which is electrically coupled with a gate or a gate conductive layer, lies on a field oxide layer. A wire bridges over the field oxide layer. It thus decreases the strength of the electrical field. The field oxide layer under the crossing wire has no drift region below. Thus the electrical field crowding effect does not occur at the junction between drift region and channel. In addition, there is no wire over the field oxide layer having the drift region below. The strength of electrical field between the drift region and the channel decreases and the breakdown voltage of high-voltage lateral double-diffused metal oxide semiconductor increase, which makes the devices work normally.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are interested to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5917222 (1999-06-01), Smayling et al.
patent: 5939753 (1999-08-01), Ma et al.
patent: 6087232 (2000-07-01), Kim et al.
patent: 6160289 (2000-12-01), Kwon et al.
Fourson George
United Microelectronics Corp.
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