Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1999-03-30

2001-05-15

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S525000

Reexamination Certificate

active

06232187

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to a semiconductor device having a reliability improved by introducing nitrogen into a part of a gate insulating film and a manufacturing method thereof.
2. Description of the Background Art
In the manufacture of semiconductor devices, it is a significant object to secure the reliability of a gate insulating film in an MOSFET (Metal Oxide Semiconductor Field Effect Transistor). One factor of deterioration of the reliability of a gate insulating film is hot carriers injected into the gate insulating film. As the size of a semiconductor device decreases, the electric field in the direction along a channel region in the semiconductor device is enhanced, and carriers present in the channel region are accelerated by the electric field and have high energy. The carriers with such high energy are hot carriers. The hot carriers having the high energy can easily be injected into the gate insulating film over the energy barrier at the interface between the semiconductor substrate and the gate insulating film.
The carriers injected into the gate insulating film are partly captured into the gate oxide film or generate a surface level, thereby changing the threshold voltage of the semiconductor device or lowering the current driving capability.
In order to prevent the reliability of a semiconductor device from degrading by the hot carriers, use of an oxynitride film as a gate insulating film has been proposed. Use of an oxynitride film for a gate insulating film improves the resistance against hot carriers as well as improves the amount of charges injected until the gate insulating film breaks down, and therefore the dopant in the gate electrode may be prevented from penetrating through the gate insulating film and diffusing within the semiconductor substrate.
Now, referring to
FIG. 69
, the structure of a conventional MOSFET will briefly be described. In a p well region
8
formed in an N type semiconductor substrate
1
, an n
+
drain diffusion region
3
a
and an n
+
source diffusion region
3
b
are formed a prescribed space apart from each other with a channel region therebetween. Adjacent to n
+
drain diffusion region
3
a
and n
+
source diffusion region
3
b
on the side of the channel region, n
−
LDD layers
2
a
and
2
b
having an LDD structure are formed. On the channel region, a gate electrode
5
is formed with a gate insulating film
4
b
formed of an oxynitride film therebetween.
A method of manufacturing such an MOSFET will briefly be described in conjunction with
FIGS. 70
to
73
.
Referring to
FIG. 70
, an element isolation insulating film
6
is formed on n type semiconductor substrate
1
by selective oxidation. Then, a p type impurity such as boron ions is implanted into n type semiconductor substrate
1
a number of times in different implantation energies to form p well
8
while controlling the threshold voltage of the MOSFET.
Referring to
FIG. 71
, a surface of n type semiconductor substrate is oxidized by thermal oxidation to form gate oxide film
4
. Then, n type semiconductor substrate
1
is subjected to thermal treatment in a nitrogen dioxide-containing atmosphere in order to nitrogenize gate insulating film
4
, and oxynitride film
4
b
results.
Now, referring to
FIG. 72
, a polycrystalline silicon film doped with phosphorus is formed on oxynitride film
4
, and a resist film patterned into a prescribed shape is formed on the polycrystalline silicon film by means of photolithography. The polycrystalline silicon film is patterned using the resist film to form gate electrode
5
. The resist film is then removed away, and using the gate electrode
5
as mask, a substance such as arsenic is implanted into p well
8
to form n
−
LDD layer
2
a
,
2
b.
Referring to
FIG. 73
, a side wall oxide film
7
is formed on a sidewall of gate electrode
5
, and then using sidewall oxide film
7
and gate electrode
5
as mask, p well
8
is implanted with arsenic to form drain diffusion region
3
a
and source diffusion region
3
b
. Then prescribed heat treatment follows to complete the MOSFET shown in FIG.
69
.
A non-volatile semiconductor memory device is one of semiconductor integrated circuit devices. Above all, an EEPROM (Electrically Erasable and Programmable Read Only Memory) which permits free programming of data as well as electrical writing and erasing is well known. In such an EEPROM, a flash EEPROM which permits batch erasing of information written therein is disclosed for example by U.S. Pat. No. 4,868,619.
In the flash EEPROM, when data is written or erased, electrons are passed through the gate insulating film by the tunnelling effect, and the electrons injected into the gate insulating film are partially captured therein or sometimes generate a surface level in the interface between the gate insulating film and the semiconductor substrate. As a result, the threshold voltage of the flash EEPROM changes, and the current driving capability is lowered. In order to restrain such degrading of the reliability of the gate insulating film, use of an oxynitride film for the gate insulating film has been proposed.
The structure of a conventional flash EEPROM using an oxynitride film for the gate insulating film will briefly be described in conjunction with FIG.
74
.
The conventional flash EEPROM has a drain diffusion region
103
a
and a source diffusion region
103
b
spaced apart from each other on a p type semiconductor substrate
101
with a channel region therebetween. On the channel region, a charge accumulating electrode
105
is formed with a gate insulating film
104
b
inbetween, and on charge accumulating electrode
105
, a control electrode
108
for electrically isolating charge accumulating electrode
105
is formed with an interlayer insulating film
107
inbetween. A sidewall oxide film
110
is formed on sidewalls of charge accumulating electrode
105
and control electrode
108
.
A method of manufacturing the flash EEPROM will briefly be described in conjunction with
FIGS. 75
to
79
.
Referring to
FIG. 75
, a surface of p type semiconductor substrate
101
is oxidized by means of thermal oxidation, and a gate oxide film is formed. Thereafter, gate oxide film is nitrogenized to form an oxynitride film
104
b
by means of thermal treatment in an atmosphere containing ammonia.
Then, referring to
FIG. 76
, on oxynitride film
104
b
formed is a first polycrystalline silicon film doped with phosphorus, on which an interlayer insulating film formed of a composite film of an oxide film and a nitride film is formed. Then, a second polycrystalline silicon film doped with phosphorus is formed on interlayer insulating film.
A resist film patterned into a prescribed shape is formed by means of photolitography on the second polycrystalline silicon film. Then, using the resist film as mask, the second polycrystalline silicon film, interlayer insulating film and the first polycrystalline silicon film are etched, the resist film is removed away, and thus control electrode
108
, interlayer insulating film
107
and charge accumulating electrode
105
are formed.
Now, referring to
FIG. 77
, a resist film
109
covering a region to be a drain diffusion region is formed, and using control electrode
108
and resist film
109
as mask, p type semiconductor substrate
101
is implanted with arsenic ions. A source diffusion region
103
b
is formed in p type semiconductor substrate
101
as a result.
Now referring to
FIG. 78
, after removal of resist film
109
, a sidewall oxide film
110
is formed on sidewalls of control electrode
108
and charge accumulating electrode
105
. Then, a resist film
111
covering source diffusion region
103
b
is formed, and using control electrode
108
and resist film
111
as mask, p type semiconductor substrate
101
is implanted with arsenic ions. As a result, a drain diffusion region
103
a
is formed in p

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