Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-01
2001-05-29
Whitehead, Jr., Carl (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S338000, C257S350000, C257S386000, C257S394000, C257S397000, C257S506000, C257S520000, C257S523000, C257S545000
Reexamination Certificate
active
06239472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to semiconductor transistor structures having improved source/drain junction performance.
2. Description of the Related Art
As the demand for faster, smaller, and more densely packed integrated circuit designs continue to increase, a greater burden is placed on design engineers to improve upon the design of standard CMOS transistors. Dominant limitations in scaling down the size of transistors are directly linked to increasing parasitic source/drain junction capacitances, tight thermal budget constraints for backend processing, hot carrier damage, and the possibility of punch-through between the source/drain as gate lengths continue to shrink. These limitations are therefore the driving force that has intensified drain engineering in high performance digital CMOS technology transistor design. Recent studies have proven that very shallow junction formation (around 0.1 micron or less) is necessary for drain engineering to be feasible in quarter-micron technology devices and below, which is common in current CMOS technology. To illustrate some of the conventional transistor devices and their associated limitations, reference is now drawn to
FIGS. 1A through 1E
.
FIG. 1A
shows a cross-sectional view of an LDD (lightly doped drain) transistor device
100
fabricated over a semiconductor substrate
102
. The LDD transistor device
100
is shown having diffusion regions
104
a
and
104
b
, which respectively define the source and drain of the transistor device
100
. Between the source and drain, a gate structure including a gate oxide
108
and a gate electrode
109
is fabricated thereon. The transistor device
100
also includes oxide spacers
110
, which are used during the formation of the lightly doped drain (LDD) regions. In this example, the substrate is a P-type substrate (but of course, it can be an N-type substrate as illustrated by the parenthesis), and the diffusion regions
104
that define the source and drain are implanted with N+ impurities. In addition, the gate structure
109
is an N+ impurity region. During the normal operation of the LDD transistor device
100
, a gate capacitance (C
gate
) is established across the gate oxide
108
. A significant component of total capacitance is the parasitic junction capacitance (C
J
) that is created at the induced depletion region between the source/drain and substrate interface.
As pictorially illustrated, the parasitic capacitance created between the source/drain and the substrate are shown as C
J1
, and C
J2
. Therefore, the total capacitance is approximately equal to “C
total
=C
gate
+C
J1
+C
J2
.” Although a gate capacitance C
gate
is required for the normal operation of the LDD transistor device
100
, the presence of the parasitic capacitance C
J1
and C
J2
has a detrimental impact upon the speed that the transistor can switch during a logic transition. That is, each time the transistor device switches between a logic state, the source/drain junction parasitic capacitance must be charged and discharged, which can unfortunately slow down the functionality of a high performance circuit.
For ease of understanding, reference is now drawn to
FIG. 1B
in which the junction capacitance C
J
between the diffusion regions
104
and the substrate
102
are pictorially illustrated about cross-section A—A. When an alternating current (AC) is applied between the junction formed by the diffusion regions
104
and the substrate
102
, the depletion region
104
′/
102
′ that is at the junction of the two materials responds to the AC signal. More specifically, the electric field (É) is plotted across the junction between the diffusion region
104
and the substrate
102
to illustrate how the parasitic capacitance C
J
at the junction is approximated.
The electric field across the junction of the diffusion region
104
is plotted in a line
106
a
having a slope that is approximately proportional to the concentration of donor atoms (N
D
) of
104
. In a like manner, the line
106
b
has a slope that is defined by the approximate concentration of acceptor atoms (N
A
) of the substrate
102
. Once the electric field is plotted, the junction capacitance C
J
is approximated to be 1/W, where W is the width of the depletion region. Therefore, if the donor concentration (N
D
) of the diffusion region
104
increases, the slope
106
a
will also increase. Similarly, if the acceptor atom concentration (N
A
) of the substrate
102
increases, the slope
106
b
will also increase. In this example, the slope of line
106
a
is greater than the slope of line
106
b
because the donor concentration of the diffusion region
104
is higher than the concentration of the acceptor atoms in the substrate
102
.
For the LDD transistor device
100
to operate properly, the concentration in the diffusion regions
104
must be greater than the concentration of the substrate
102
. For example, the impurity concentration of P+ and N+ diffusion regions
104
are typically in the range of between about 1×10
19
atoms cm
−3
and 1×10
21
atoms cm
−3
. The impurity concentration of the substrate
102
on the other hand, typically ranges between about 1×10
16
atoms cm
−3
and about 5×10
17
cm
−3
. As a result, it is generally not possible to decrease the large parasitic junction capacitance C
J
in an LDD transistor device, which necessarily limits its application in high performance applications (or simply slows down the circuit due to capacitive loading).
As mentioned above, another problem with the continued shrinking of transistor devices is the ability to meet tight backend processing thermal budget requirements. As is well known, a thermal budget is generally determined by calculating the total number of heat treatments and the time of those heat treatments that must be performed during the formation of the various layers of an integrated circuit device. By way of example, when an integrated circuit device requires a set number of layers, a thermal budget places a limitation on the heat treatments, such that dopant impurities do not over-diffuse into the substrate. For example, several types of dielectric deposition techniques require the application of heat annealing operations in order to adequately cure the dielectric materials. Such dielectric materials include spin-on glass (SOG), wherein the quality is improved by performing a certain type of heat anneal treatment. Additional heat treatments are also commonly required to cure certain types of conductive vias. Unfortunately, all of these heat treatments add to an already tight thermal budget.
FIG. 1C
shows an ideal diffusion profile
113
a
which must be maintained after all of the backend thermal processing is performed. However, when the thermal budget is set too tight, the diffusion regions
104
may subsequently drop into the substrate down to profile lines
113
b
, thereby causing the depletion regions
114
a
′ and
114
b
′ to be formed. As a result, the source and drain regions will no longer be isolated from one another, and will “punch-through” to electrically connect the source and drain. In other words, when punched-through occurs in a transistor device, the transistor will no longer operate in its intended manner. Unfortunately, the possibility of having the punched-through effect occurring in modem transistor devices is increasing as the demand for smaller and smaller transistor devices continues to grow. As a result, very stringent thermal budget requirements are placed on all backend processing, which therefore increase the complexity and cost of fabrication.
FIG. 1D
is a pictorial illustration of the electric field (É) that is created when conduction between the source and drain occurs during an ON state. As further mentioned above, another problem with conventional LDD transistor devices is that of hot carrier generation, that ar
Jr. Carl Whitehead
Martine Penilla & Kim LLP
Philips Electronics North America Corp.
Warren Matthew E
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