Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-04
2001-11-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S598000, C438S926000
Reexamination Certificate
active
06319818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly to methods for planarizing patterned conductors using a pre-mask checkerboarding of wiring lines.
2. Background Art
Planarization methods in the fabrication of semiconductor devices are disclosed in U.S. Pat. No. 5,278,105 issued Jan. 11, 1994 to Eden et al. entitled SEMICONDUCTOR DEVICE WITH DUMMY/FEATURE IN, ACTIVE LAYERS that discloses a design and fabrication method for a semiconductor device that allows different types of devices to be processed using the same process steps.
U.S. Pat. No. 5,292,689 issued Mar. 8, 1994 to Cronin et al. entitled METHOD FOR PLANARIZING SEMICONDUCTOR STRUCTURE USING SUBMINIMUM FEATURES discloses a method for fabricating planarized semiconductor structures that are prepared using a plurality of subminimum polysilicon vertical pillars by chemical vapor deposition to prevent depressions in the planarized surface.
U.S. Pat. No. 5,539,240 issued Jul. 23, 1996 to Cronin et al. entitled PLANARIZED SEMICONDUCTOR STRUCTURE WITH SUBMINIMUM FEATURES also discloses planarized semiconductor structures having subminimum vertical pillars to prevent depressions in the planarized surface.
The IBM Technical Disclosure Bulletin, Vol. 26, No. 10A, March 1984 at page 4995 by W. M. Goubau entitled PLANARIZATION OF CONDUCTING SURFACES discloses a planar coating technique using a wiring pattern with evenly spaced, space-filling conductors.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved planarization method for patterned conductors.
Another object of the present invention is to provide an improved planarization method for use with polysilicon conductors, local interconnect and Back End Of Line (BEOL)) wiring.
Still another object of the present invention is to provide an improved planarization technique incorporating a pre-mask fabrication checkerboarding of wiring lines.
Other features, advantages and benefits of the present invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory but are not to be restrictive of the invention.
The accompanying drawings which are incorporated in and constitute a part of this invention and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 5278105 (1994-01-01), Eden et al.
patent: 5292689 (1994-03-01), Cronin et al.
patent: 5539240 (1996-07-01), Cronin et al.
patent: 5888900 (1999-03-01), Mizuno
patent: 5915201 (1999-06-01), Chang
IBM Technical Disclosure Bulletin, vol. 26, No. 10A, Mar. 1984 p. 4995, Planarization of Conductor Surfaces, W. M. Goubau.
Berezny Nema
Bowers Charles
Goodwin John J.
International Business Machines - Corporation
LandOfFree
Pattern factor checkerboard for planarization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern factor checkerboard for planarization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern factor checkerboard for planarization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2569842