Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-03-31
2001-11-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S113000, C326S086000, C326S056000
Reexamination Certificate
active
06313661
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuitry; more particularly, to interface circuits useful for transmitting signals between an integrated circuit (IC) and an external bus, circuit or system.
BACKGROUND OF THE INVENTION
Input/output (I/O) buffer circuits are generally well known in the semiconductor and computer arts. Early semiconductor processes were designed to operate in the voltage range of zero to five volts. In recent years, a new low voltage integrated circuit standard based on a 3.3-volt nominal power supply has become prevalent in semiconductor devices. Since the trend toward reduced power consumption devices will surely continue, is likely that future integrated circuits will be based on an even lower supply voltage standard (e.g., 1.8 volts). As one might expect, problems arise when lower voltage integrated circuits interface with legacy buses and older devices that operate with higher supply voltage potentials.
Modem complementary metal-oxide semiconductor (CMOS) technologies frequently operate between the power supply voltage (V
CC
) of 3.3 volts and ground (V
SS
). In CMOS technology, PMOS transistors are fabricated with p-type source and drain regions formed in an n-type well region. The n-type well region is normally disposed in a p-type semiconductor substrate. NMOS transistors are fabricated with n-type source and drain regions formed in the p-type substrate. These two different regions for PMOS and NMOS transistor formation are illustrated in FIG.
1
. By way of example,
FIG. 1
shows N-well
12
formed in P-substrate
11
. In CMOS digital systems, I/O buffers are often designed to operate in mixed voltage environments. For example, in a typical computer system the central processor, I/O controller, or other chips may communicate with an assortment of peripheral devices via a Peripheral Component Interconnect (PCI) bus.
FIG. 2
illustrates such a mixed voltage system comprising a processor
20
that includes I/O buffer circuitry
22
connected to bus
25
. In this system, integrated circuits with 5V and 3.3V driving capabilities are commonly coupled to the PCI bus.
Two types of operations are commonly encountered in systems such as that shown in FIG.
2
. The first operation arises when the driver is required to drive a high voltage (5V) onto the bus. The second type of operation is where the driver has to tolerate a high voltage (V
BUS
=5V), but drives only a lower voltage (V
CC
=3.3V) at its output node (V
PAD
). In the case where the driver must tolerate a high input voltage but only drives a lower output voltage, a number of detrimental effects can occur. First, the PN junction formed by the p-type drain region and the N-well region associated with the lower voltage (3.3V) driver PMOS pull-up transistor can become forward biased. This happens when the output pad of the buffer, which is connected to the drain of the PMOS pull-up transistor, experiences a high voltage (5V) signal applied from the common external bus. With the PN junction forward biased, a low impedance path is created from the high voltage external bus (V
BUS
=5V) to the internal lower voltage power supply rail (V
CC
=3.3V). Additionally, the high voltage applied to the output pad of the buffer can cause electrical stress damage to various internal nodes of the lower voltage driver circuit. For obvious reasons, it is desirable to eliminate both of these harmful effects.
One prior art approach described in U.S. Pat. No. 5,892,377 teaches a high voltage tolerant buffer circuit that utilizes an additional high-voltage supply (e.g., 5V). The additional supply line is provided on-chip to bias the N-well of the pull-up PMOS output drivers. Since the N-well is typically hard wired to a signal (V
BUS
) having a voltage that is higher than V
CC
, body effects may be introduced that raise the therehold voltage (|V
TP
|) of the PMOS transistors. This, in turn, reduces the strength of the PMOS driver, which means that a much larger PMOS device size must be utilized as compensation. Besides the area penalty of a larger PMOS transistor, a major drawback of this approach is the requirement for an additional internal high-voltage supply.
There have been several attempts to design a high voltage tolerant buffer circuit that operates from a single supply. One notable example is disclosed in U.S. Pat. No. 5,381,061, which teaches the use of a high potential level pseudorail coupled at the N-well of the PMOS output pull-up transistor. The problem with this, and similar designs, is the creation of a so-called “dead zone” associated with the input voltage range between V
CC
−|V
TP
| and V
CC
+|V
TP
|. Within this range, the buffer does not function properly; that is, a leakage path exists between the output node (V
PAD
) and V
CC
.
U.S. Pat. No. 5,661,414 discloses a circuit solution to the “dead zone” problem. However, this solution requires a large, complicated circuit that occupies a significant amount of extra silicon area.
Therefore, what is needed is a circuit solution that overcomes the foregoing detrimental problems and which does not require an additional high voltage power supply and which is not unduly costly in terms of silicon area.
SUMMARY OF THE INVENTION
The present invention comprises an input/output (I/O) buffer circuit having an output node tolerant of an externally applied high voltage signal. The I/O buffer circuit is powered by a lower voltage supply potential and comprises a n-well region associated with PMOS transistors. A bias generation circuit generates a reference voltage at an internal node of the I/O buffer circuit. A PMOS pull-up transistor is coupled between the lower voltage supply potential and the output node. A NMOS pull-down transistor is coupled between the output node and a ground reference potential. In addition, first and second PMOS charging transistors are included, each of the first and second PMOS charging transistors having its gate coupled to the internal node. The first PMOS charging transistor is coupled between the output node and the gate of the PMOS pull-up transistor, and the second PMOS charging transistor is coupled between the output node and the n-well region.
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patent: 5570043 (1996-10-01), Churchill
patent: 5576635 (1996-11-01), Partovi et al.
patent: 5661414 (1997-08-01), Shigehara et al.
patent: 5764077 (1998-06-01), Andresen et al.
patent: 5864243 (1999-01-01), Chen et al.
patent: 5892377 (1999-04-01), Johnston et al.
patent: 6084431 (2000-07-01), Shigehara et al.
patent: 06140911-A (1994-05-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Paik Steven S.
Tokar Michael
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