Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-18
2001-11-13
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S263000, C438S264000, C438S265000
Reexamination Certificate
active
06316316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices, and more specifically to the semiconductor fabrication process of memory devices. The invention proposes a method of forming high density and low power flash memories with a high capacitive-coupling ratio.
BACKGROUND OF THE INVENTION
Memory devices are one of the most important devices for storing of data and information. By storing data electrically in the memory devices, the data can be accessed with ultra high speed for various applications. The progress in memory device fabrication technology has made memories become a highly reliable and valuable device for a great amount of data reading and data writing access within an extremely short time. Various types of memories have been developed for a variety of applications like computation and communications systems.
An ideal storage device must have several characteristics. Numerous important applications of memory devices are specified with highly reliable and high speed operations. Low cost is needed for the explosively increasing demand on the more storage capability with a great number of storage units. High performance and high density are both important factors for performing reliable and high speed operations with least volume needed for the storage devices. Low power dissipation are highly demanded for providing longer operation time or greener operations especially for portable devices with limited capacity of power supply. Non-volatile or least refreshing characteristics is needed for both reliable, safety, and low power data storage.
Flash memory has became a valuable choice in the market of portable electrical devices and systems. High density and low power flash memories are required for future portable computer and telecommunication applications. In the article “Low Voltage NVG™: A New High Performance 3V/5V Flash Technology for Portable Computing and Telecommunications Applications” (in IEEE Transactions on Electron Devices, Vol. 43, No. 9, p. 1510, 1996), A. Bergemont et al. introduce a new concept for low voltage NOR Virtual Ground (NVG™) flash memory with a fast access time. It is mentioned that the portable telecommunications and computing market has become a major driving force in semiconductor IC (Integrated Circuits) design and technology. The growing market requires low power, high density, and electrically re-writable non-volatile memories, either embedded or stand-alone. Flash memory is another choice other than EEPROM (Electrically Erasable and Programmable ROM) because of its small size and improved reliability. New concepts and modifications of NVG™ flash memory is proposed in the work with thinner field oxide in the array to improve gate coupling of cells and result in faster programming and erase.
The capacitive-coupling ratio is a vital factor in determining the functional characteristics of the flash memory. For achieving a high density and low power flash memory, a cell structure with contactless array and high capacitive-coupling ratio have been proposed. H. Shirai et al. developed a self-aligned memory cell for 256 Mbit flash memory in 1995 (in “A 0.54 &mgr;m
2
Self-Aligned, HSG Floating Gate cell (SAHF Cell) for 256 Mbit Flash memories”, in IEDM Tech. Dig., p. 653, 1995). Hemispherical-grained (HSG) polysilicon is applied to floating gate to extend the upper surface area double that of the floating gate in comparison with the conventional ones. A high capacitive-coupling ratio of 0.8 and buried n
+
diffusion layers which are self-aligned to the floating gate polysilicon are realized in their work.
However, a contactless array with a high capacitive-coupling ratio is difficult to be manufactured in the conventional process. Y. S. Hisamune et al. have described in the work “A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories” (in IEDM Tech. Dig., p.19, 1993) that a great number of total process-steps are needed for manufacturing a memory cell. The complicate process-steps in the conventional fabrication process of flash memory greatly increase the cost and efforts in achieving a high capacitive-coupling ratio.
A thinner tunnel oxide in flash memory is also recognized as an important factor to enhance the electron injection efficiency. But it is difficult to fabricate a thin tunnel oxide with a high electron injection efficiency and a large charge-to-breakdown for low power nonvolatile memories. The inventor of the present invention has reported that scaling down the thin tunnel oxide for lower voltage operation may face limitations in defect density, retention due to stress-induced leakage and charge leakage due to direct tunneling (in “Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon” by S. L. Wu et al., in IEEE Transactions on Electron Devices, Vol. 43, No. 2, p. 287, 1996). For the thicker polyoxide which uses the rough polysilicon/oxide interface as an efficient electron injector, the very large electron trapping rate and the writing-erasing memory window closing due to electron trapping will limit the memory endurance. Moreover, the reduction in thickness does not give a proportional reduction in the programming voltage because of the decrease on the electric field enhancement factor with the scaling-down of the thickness of polyoxide. The characteristics of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on Si substrate (TOPS) are studied in detail in the paper.
SUMMARY OF THE INVENTION
The present invention propose a method of forming flash memories. The method can provide high density and low power flash memories with a high capacitive-coupling ratio. A simpler process than the conventional process in fabricating flash memories is provided. A thin tunnel oxide is provided with increased effective area to have a raised electron injection efficiency, and a large charge-to-breakdown for low power non-volatile memories can be achieved.
The method in the present invention for forming a memory cell includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. The pad oxide layer is formed on a region uncovered by the isolation region on the semiconductor substrate. The first nitride layer formed over the pad oxide layer. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed on a region uncovered by the gate region and the isolation region on the semiconductor substrate. A sidewall structure is formed on the gate region and the semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer on a region uncovered by the sidewall structure, the gate region, and the isolation region. The first type dopants are driven in at the same time.
The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of the substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate. A second thermal process is performed to form a tunnel oxide layer on the rugged surface. Next, a first conductive layer is formed over the semiconductor substrate. A portion of the first conductive layer is removed to define a floating gate. A dielectric layer is formed over the semiconductor substrate and a second conductive layer is then formed over the semiconductor substrate as a control gate.
In addition, a step of depositing an undoped hemispherical grain (HSG) silicon film on the first conductive layer can be added after the first conductive layer is formed. The surface area of the first conductive layer as a floating gate can be significantly raised.
REFERENCES:
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Chaudhuri Olik
Rao Shrinivas H.
Texas Instruments--Acer Incorporated
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