Method of forming high density buried bit line flash EEPROM...

Details Method of forming high density buried bit line flash EEPROM... Method of forming high density buried bit line flash EEPROM...

1999-06-04

2001-07-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06255167

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory process, and more specifically, to a structure of high-density buried bit line flash EEPROM memory cells with a shallow trench-floating gate.
BACKGROUND OF THE INVENTION
In recent years, the development of portable telecommunications and laptop computers has become a major driving force in the design and technology of semiconductor ICs. This growing market requires low power, high-density and electrically rewritable nonvolatile memories. Electrically erasable programmable read only memories (EEPROM) are electrically erased on a byte-by-byte basis is one choice. However, the cell size of this memory is too large for application, and thus the flash memory is another choice because of its small size and highly reliability.
For achieving a high density memory device, Kazerounian et al., introduced a virtual ground concept using alternative metal virtual ground (AMG) to fabricate EPROM in the paper by R. Kazerounian, et al., titled “Alternate Metal Virtual Ground EPROM Array Implemented in a 0.8 &mgr;m Process for Very High Density Applications”, IEDM Tech. Dig., p. 311, 1991. The synoptic layout and cross-sectional of this memory array are shown in
FIGS. 1
a
-
1
b,
The front end of the process is a standard n-well CMOS process. After LOCOS field oxidation and the EPROM gate a layer of the polysilicon
10
is deposited, and an ONO dielectric layer
15
is then formed on the top of the polysilicon
10
. The ONO 15/poly-Si 10 is then patterned in elongated strips across each segment. Subsequently, a self-aligned arsenic implant form bit lines
20
. An oxidation process combined with the CMOS gate oxidation process is done to form a gate oxide and to grow a bit line oxide. The process continues with doped polysilicon
25
and tungsten silicide
35
deposition. A self-aligned stack gate etch process is employed to define word line
25
and floating gate cell
40
. The advantages of this array are the reduction of drain turn-on induced punchthrough and the allowance of scaling of effective channel length to as low as 0.25 &mgr;m.
Later, the virtual ground concept then was applied to manufacture low voltage NOR virtual ground power flash memories by Bergemont, et al., to develop a flash memory with a fast access time. This is disclosed in the reference by A. Bergemont, et al., “Low voltage NVGTM: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications”, IEEE Trans. Electron Devices, ED43, p. 1510, 1996. The architecture of NVGTM is similar to AMG EPROM having a feature where one metal bit-line is shared between two columns of cells. These metal bit-lines are stripped to every other diffusion bit-line (stripped, continuous bit lines) through the selected transistors.
SUMMARY OF THE INVENTION
The foregoing prior art demonstrate some problems, such as the punch-through issue or the narrow space between the adjacent bit lines and the short channel effect. Thus in the present invention, a method of fabricating buried bit line flash EEROM cells using recessed silicon trench floating gates for suppressing the short channel effect is disclosed. The method comprises the following steps. First, a doped polysilicon layer with conductive impurities, such as phosphorus with concentrations of about 5×10
10
-5×10
21
/cm
3
, is formed on the silicon substrate. Then, an anti-reflection coating (ARC) layer is formed on the doped polysilicon layer to improve the lithographic resolution. After coating a patterned mask on the ARC layer to define a plurality of buried bit line regions, a dry etch is performed to etch the unmasked regions till the silicon substrate is slightly recessed to form shallow trenches of about 50-600 nm in depth. Subsequently, the photoresist is stripped, and a gate dielectric layer is formed of a oxynitride layer of about 3-25 nm in thickness is thermal grown on the surface of the recessed silicon substrate. In the meantime, a poly-oxide layer on the sidewall of the doped polysilicon layer is formed. In addition, the buried bit lines are also formed where the bit lines include the remaining doped polysilicon layer and the layer beneath it due to the impurities driving in. After refilling a plurality of trenches with an in-situ doped silicon layer, a planarization process such as CMP is done to form a plain surface using the ARC layer as an etching stop layer. A stacked ONO layer of about 5-30 nm is then deposited as an interpoly dielectric layer. Finally another n+doped polysilicon layer is formed and patterned to form the word lines.


REFERENCES:
patent: 5495441 (1996-02-01), Hong
patent: 5529943 (1996-06-01), Hong et al.
patent: 5635415 (1997-06-01), Hong
patent: 6048765 (2000-04-01), Wu

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