Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-19
2001-12-11
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S376000
Reexamination Certificate
active
06329257
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory technology and more particularly to a method and system for controlling the doping profile of a source in a flash memory cell.
BACKGROUND OF THE INVENTION
A conventional flash memory cell includes a gate stack, a source, a drain, and a channel disposed between the source and the drain. To form a conventional memory cell, a tunnel oxide is grown or deposited on a semiconductor substrate. Typically, the gate stack is formed on the tunnel oxide and reoxidized. Reoxidation exposes the gate stack to an oxidizing agent at a high temperature, growing a layer of oxide on the gate stack. The reoxidation of the gate stack of the conventional memory cell improves erase characteristics.
After the growth of the oxide layer is completed in reoxidation, the source and drain are implanted and annealed. Annealing electrically activates and diffuses the source and drain implants.
A conventional memory cell formed using the above-described process includes a bird's beak shaped tunnel oxide and a source dopant which decreases in concentration closer to the center of the gate stack. The “bird's beak” shaped tunnel oxide is thicker near the edge of the gate stack than closer to the center of the gate stack. Note that the edge is actually a three dimensional face of the gate stack. Consequently, as used herein, edge is a three dimensional face. Only closer to the center of the floating gate does the oxide have a relatively constant thickness. The concentration of source dopant is highest at the surface of the semiconductor adjacent to the gate stack in part as a result of the annealing step. Consequently, the concentration of source dopant decreases toward the center of the gate stack.
Although the conventional memory cell functions, erase of the conventional memory cell may not be well controlled. To erase a conventional memory cell, tunneling of charge carriers between the floating gate and the source is used. Tunneling of charge carriers between the floating gate and the source depends on the thickness of tunnel oxide through which the charge carriers tunnel and on the doping profile of the source. Both the thickness of the tunnel oxide and the concentration of the source dopant vary under the gate stack. The appropriate combination of tunnel oxide thickness and source doping profile may be difficult to control. Tunneling of charge carriers between the floating gate and the source is, therefore, difficult to control. As a result, the erase characteristics of conventional memory cells may vary between cells on the same semiconductor.
Accordingly, what is needed is a system and method for better controlling erase characteristics. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for controlling a characteristic of at least one memory cell on a semiconductor having a surface. The at least one memory cell includes a gate stack, a source, and a drain. In one aspect, the method and system comprise providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system comprise a memory cell on a semiconductor having a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.
According to the system and method disclosed herein, the present invention allows the erase characteristics of the memory cell to be better controlled, thereby increasing overall system performance.
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Luning Scott D.
Sobek Daniel
Thurgate Timothy J.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Pham Hoai
Sawyer Law Group LLP
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