Self aligned contact using spacers on the ILD layer sidewalls

Details Self aligned contact using spacers on the ILD layer sidewalls Self aligned contact using spacers on the ILD layer sidewalls

1999-02-18

2001-05-22

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S595000, C438S639000, C438S702000

Reexamination Certificate

active

06235593

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically to a fabrication sequence used to from a self aligned contact (SAC) to a substrate for a metal oxide semiconductor field effect (MOSFET).
2) Description of the Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same devices. These objectives have been successfully addressed by the ability of the semiconductor industry to practice micro-miniaturization, or to fabricate semiconductor devices with sub-micron features. Several fabrication disciplines, such as photolithography, as well as dry etching, have allowed micro-miniaturization to be realized. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist films, have allowed the attainment of sub-micron images in photoresist films, to be routine achieved. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist films, to be successfully transferred to underlying materials used for the fabrication of semiconductor devices.
In addition to advances in semiconductor fabrication disciplines, several device structural innovations have also contributed to the quest for higher performing, lower cost, semiconductor devices. For example, the use of a self-aligned contact (SAC), procedure allows the amount of source and drain contact area to be reduced, thus allowing smaller devices to be constructed, resulting in faster, as well as lower cost devices, to be realized. The SAC procedure, using a sub-micron ground rule, opens a sub-micron region in an insulator layer, exposing an underlying source and drain region. However only a portion of the sub-micron SAC opening is used to expose the underlying source and drain region, with the remainder of the sub-micron SAC opening overlapping an adjacent polysilicon gate structure. Therefore the source and drain contact region is smaller then the SAC opening. If the contact opening to the source and drain was to made entirely overlaying the source and drain region, the source and drain region would have to be designed larger, to accommodate the fully landed contact hole opening, thus resulting in a undesirable, larger semiconductor device. In addition to the cost and performance benefits of devices fabricated using the SAC procedure, a dielectric sidewall spacer can also be used, allowing the SAC opening to be created, exposing the insulator sidewall of a polysilicon gate structure.
As shown in
FIG. 4
, a problem the inventor has found is that keyholes
124
are formed in ILD layers
36
when the spacing
62
between conventional spacers
110
is small.
FIG. 4
shows gates
24
, which can comprise several layers, with conventional spacers
110
formed on the sidewalls. Conventional spacers
110
have a width between 800 and 2000 Å. A substrate
10
has STI regions
20
formed therein. A self aligned contact (SAC) plug
54
is formed to contact the substrate. The poly lines
24
are spaced closer in areas away from the SAC plug
54
.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,648,291 (Sung) shows a spacer formed on the sidewalls of contact.
U.S. Pat. No. 5,565,372 (Kim) shows a contact having a spacer.
U.S. Pat. No. 5,766,992 (Chou et al.) shows a contact process with extra SiN spacers over the gate.
U.S. Pat. No. 5,731,236 (Chou et al.) and U.S. Pat. No. 5,807,779 (Liaw) show other self aligned contact (SAC) processes.
SUMMARY OF THE INVENTION
It is an object of this invention to use thin interlevel dielectric spacers, on the sides of interlevel dielectric layer and a polysilicon gate structure, of a MOSFET device, to improve the insulator integrity in the sub-micron diameter self aligned contact (SAC) opening.
It is yet another object of this invention to create a self aligned contact (SAC) structure to a source or drain region of a MOSFET device, featuring a sub-micron diameter, self aligned contact (SAC) opening in a thick interlevel insulator layer, with the sub-micron diameter, SAC opening.
It is another object of the invention to form IDL spacers on a self aligned contact (SAC) between gate structures and simultaneously form IDL spacers on a contact without gate structures.
To accomplish the above objectives, the present invention provides a method of manufacturing a self-aligned contact (SAC) that forms spacers on the sidewalls of the interlevel dielectric layer. This contrasts with the prior art that only forms spacers on the sidewalls of the gate structure, not on the sidewalls of the interlevel dielectric layer. The invention also simultaneously forms a borderless contact with spacers. The method includes the following steps.
A gate dielectric layer is formed on the substrate. A conductive layer is formed over the gate oxide layer. The conductive layer is preferably comprised of a polysilicon layer and an overlying polycide layer. A cap layer is formed over the conductive layer. The cap layer and the conductive layer are patterned to form spaced gate structures on the substrate. The spaced gate structures are spaced apart between about 0.15 and 0.35 &mgr;m. Next, ions are implanted ions into the substrate adjacent to the gate structures to form LDD regions in the substrate. An optional liner layer is preferably composed of Silicon oxynitride, SiO
2
or silicon nitride, can be deposited over the substrate and the gate structures. An interlevel dielectric layer is deposited over the substrate and gate structures.
The interlevel dielectric layer and the liner layer and the cap layer are etched to form a contact hole that exposes the LDD region between the gate structures and removes a portion of the cap layer. The contact hole has sidewalls of the interlevel dielectric (ILD) layer. An interlevel dielectric spacer layer is formed over the interlevel dielectric layer. The sidewalls of the contact hole and on the LDD region.
In a key step, the interlevel dielectric spacer layer is anisotropically etched forming a top spacer on the sidewalls of the upper opening and a bottom spacer on the lower opening. The top and bottom spacers are not connected and are two separate distinct spacers. A contact plug is formed to fill the contact hole and electrically contacting the LDD region.
The invention's method of fabrication of a self aligned contact (SAC) uses thin interlevel dielectric spacers. The present invention provides a method of manufacturing a self-aligned contact (SAC) that forms top spacers on the sidewalls of the interlevel dielectric layer, and bottom spacers on the sidewalls of the gate structure. The invention provides a preferred embodiment for forming a borderless contact with sidewall spacers.


REFERENCES:
patent: 5268330 (1993-12-01), Givens et al.
patent: 5565372 (1996-10-01), Kim
patent: 5648291 (1997-07-01), Sung
patent: 5677231 (1997-10-01), Maniar et al.
patent: 5728595 (1998-03-01), Fukase
patent: 5731236 (1998-03-01), Chou et al.
patent: 5766992 (1998-06-01), Chou et al.
patent: 5792703 (1998-08-01), Bronner et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5981369 (1999-11-01), Yoshida et al.
patent: 6015730 (2000-01-01), Wang et al.
Wolf et al., “Silicon Processing for the VLSI Era, vol. 1-Process Technology”, Lattice Beach, 1986, pp. 384-385.

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