Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-29
2001-10-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S105000, C438S520000, C438S931000
Reexamination Certificate
active
06297100
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of Japanese Patent Applications No. 10-278227 filed on Sep. 30, 1998 and No. 11-184264 filed on Jun. 29, 1999, No. 11-264329 filed on Sep. 17, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a silicon carbide (SiC) semiconductor device, particularly to an insulation gate type field effect transistor such as a vertical power MOSFET for high power applications, and to a method of manufacturing the same.
2. Description of the Related Art
The applicant of the present invention proposes a planar type MOSFET capable of improving channel mobility to reduce an ON resistance in JP-A-10-308510 published on Nov. 17, 1998.
Referring to
FIG. 12
, the planar type MOSFET has an n
+
type semiconductor substrate
1
made of SiC and having a main surface
1
a
at an upper side of the figure and a back surface
1
b
at a lower side of the figure. An n
−
type epitaxial layer (herebelow, referred to as an epi-layer)
2
made of SiC and having a dopant concentration smaller than that of the substrate
1
is disposed on the main surface
1
a
of the substrate
1
.
Several p type base regions
3
are provided in specific surface portions of the n
−
type epi-layer
2
with a specific depth. The p type base regions
3
include boron (B) as a dopant with a dopant concentration of approximately 1×10
17
cm
−3
or more. Several n
+
source regions
4
are formed in specific surface portions of the p type base regions
3
with a depth shallower than that of the p type base regions
3
. An n
−
type SiC layer
5
extends in the surface portions of the p type base regions
3
to connect the n
+
type source regions
4
and the n
−
type epi-layer
2
. The n
−
type SiC layer
5
is epitaxially grown on the substrate
1
to have a
4
H,
6
H,
15
R or
3
C crystal structure. A channel is formed in then n
−
type SiC layer
5
when the device is operated. Herebelow, the n
−
type Sic layer
5
is referred to as a surface channel layer.
The surface channel layer
5
includes nitrogen (N) as a dopant with a dopant concentration in a range of, for example, 1×10
15
cm
−3
to 1×10
17
cm
−3
, which is lower than those of the n
−
type epi-layer
2
and the p type base regions
3
, thereby realizing a low ON resistance. A part of the n
−
type epi-layer
2
extending between the p type base regions
3
is a so-called J-FET portion
6
.
A gate oxide film
7
is formed on the surface channel layer
5
and on the n
+
type source regions
4
by thermal oxidation, and a gate electrode
8
is formed on the gate oxide film
7
. The gate electrode
8
is covered with an insulation film
9
made of LTO (Low Temperature Oxide). A source electrode
10
is formed on the insulation film
9
in contact with the n
+
type source regions
4
and the p type base regions
3
. A drain electrode
11
is formed on the back surface
1
b
of the substrate
1
.
This planar type MOSFET is operated in an accumulation mode at which a channel is induced without inverting the conductive type of the surface channel layer
5
. In the accumulation mode, the surface (channel) mobility is less influenced by the electric field (gate) and surface effects (MOS interface) compared to the inversion mode due to a large depth of the channel (about 5-10 times). Therefore, channel mobility of the MOSFET is large, so that the ON resistance is reduced as compared to that of a MOSFET, which is operated in an inversion mode at which the conductive type of the surface channel layer is inverted. However, when B is used as a dopant for forming the p type base regions
3
, B is diffused during heat treatment, such as during activation annealing as disclosed in U.S. Pat. No. 5,710,059. Diffused B can narrow the width of the J-FET portion, and undesirably invert the conductive type of the surface channel layer
5
contacting the p type base regions
3
.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above limitations. A first object of the present invention is to prevent a width of a J-FET portion extending between base regions from being narrowed by diffused impurities. A second object of the present invention is to prevent inversion of a surface channel layer conductive type by diffused impurities.
In the cases where the n
−
type epi-layer
2
is epitaxially grown and where the p type base regions
3
are formed by ion implantation of B-impurity atoms, it is believed that carbon vacancies are responsible for the extended diffusion of B. The carbon vacancies are produced during the ion implantation process. Also a kick-out mechanism which explains B at a Si-lattice site and an interstitial Si complex (a highly mobile complex) is responsible for transient enhanced diffusion of B, thereby causing the limitations described above. The present invention overcomes these limitations based on the consideration described above.
Briefly, according to the present invention, a second conductive type base region is formed in a specific surface portion of a first conductive type semiconductor layer. The formation of the base region is performed by forming an impurity implantation layer by implanting ions of an inactive ion species into at least one of the specific surface portion for forming the base region and a J-FET portion, and second conductive type impurities of an active ion species into the specific surface portion; and activating the second conductive type impurities to form the base region contacting the J-FET portion. Preferably, the inactive ion species is C (carbon) and the active ion species is B (boron). Preferably, the implantation of the inactive ion species is carried out before the implantation of the second conductive type impurities.
Accordingly, carbon vacancies in the J-FET portion or in the specific surface portion for the base region can be eliminated by implanted ions of the inactive ion species to inhibit the diffusion of the second conductive type impurities. As a result, the width of the J-FET portion is not narrowed, and a length of a channel region produced on the J-FET portion is prevented from increasing.
Ions of the inactive ion species may be implanted into a surface channel layer formed on the base region. Accordingly, the second conductive type impurities are prevented from being diffused into the surface channel layer, thereby preventing inversion of the surface channel layer conductive type in an accumulation type semiconductor device.
The second conductive type impurities may be implanted into a part of the specific surface portion using a mask covering a surface between a source region and the J-FET portion. The implanted second conductive type impurities are diffused to exist entirely in the specific surface portion for forming the base region when the second conductive type impurities are activated. In this case, because the surface between the source region and the J-FET portion where the surface channel layer is to be formed does not undergo the ion implantation of the second conductive type impurities, the surface channel layer can be formed with high crystallinity.
In the silicon carbide semiconductor device according to the present invention, the inactive ion species is included in at least one of the base region and a portion contacting the base region. The portion contacting the base region is the J-FET portion, the surface channel layer, or the like. Accordingly, the diffusion of the second conductive type impurities is suppressed. When the inactive ion species is included in one of the base region and the J-FET portion, the width of the J-FET portion is prevented from being decreased. When the inactive ion species is included in the surface channel layer, the conductive type of the surface channel layer is prevented from being inverted.
REFERENCES:
patent: 3982262 (1976-09-01), Karats
Kumar Rajesh
Naito Masami
Nakamura Hiroki
Takeuchi Yuichi
Chaudhari Chandra
Denso Corporation
Pillsbury & Winthrop LLP
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