Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-13
2001-07-24
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C257S413000
Reexamination Certificate
active
06265259
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a complementary metal oxide semiconductor field effect transistor (CMOSFET).
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in semiconductor technologies. For deep sub-micron high performance MOS ULSI application, as suggested in the reference B. Davari, in IEDM Tech. Dig., p.555, 1996, the dual poly gate CMOS technology (p+ poly gate for PMOSFET and n+ poly gate for NMOSFET) is necessary. However, as mentioned in Y. Taur, et al., in IEDM Tech. Dig., p. 901, 1992, the effect of boron penetration through the thin gate oxide into silicon substrate will degrade the device performance. There are several methods to suppress the boron penetration effects, such as (1) N
2
O nitridation of thin gate oxide suggested in reference E. Hasegawa, et al., in IEDM Tech. Dig., p327, 1995, (2) the heavy nitrogen implantation (dosage>4E 15 cm-2) into poly-Si suggested in reference S Shimizu, et al., in IEDM Tech. Dig., p.67, 1994, and (3) the stacked-Si layer as gate material suggested in S. L. Wu, et al., in IEDM Tech. Dig., p329, 1993, etc.
Although the heavy nitrogen implantation into poly-Si layer could effectively suppress the boron penetration effects, the sheet resistance of poly gate will be largely increased with increasing the nitrogen dosage for both n+ and p+ poly gates, especially for the nitrogen dosage larger than 4E15 cm
−2
. This is shown in the reference S. Shimizu, et al., J. Appl. Phys., vol. 35, p.802, 1996.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method to fabricate dual gate CMOS devices without boron penetration.
A second object of the present invention is to provide a method to fabricate dual gate CMOS devices for suppressing boron penetration without serious side effects.
This invention discloses a method to fabricate dual gate CMOS devices with gate structures having diffusion barriers for suppressing boron penetration, a phenomenon that boron atoms doped in gate electrode penetrate into the gate oxide and substrate. Firstly, a gate oxide layer is formed on a semiconductor substrate. Thereafter, a first silicon layer, a second silicon layer, and a third silicon layer are successively stacked on the gate oxide layer, and N type dopant is in situ doped into the second silicon layer. After the three silicon layers are stacked, the gate structure is formed by etching the three stacked silicon layers, and then source/drain structures with LDD regions are subsequently formed in the substrate by ion implantation processes. Finally, a thermal treatment is performed to form shallow source and drain junction in the substrate, thereby achieving the structure of the CMOS device. Meanwhile, the N type dopant is driven to the boundaries of stacked silicon layers of gate structure so as to act as diffusion barriers for suppressing boron penetration.
Since the diffusion barriers of the invention are not formed by implanting nitrogen ions, the benefits could be summed up according to the following: (1) The device reliability could be improved by using the dual poly gate CMOS technology; (2) the boron penetration effects in p+ poly gate pMOSFETs could be fully suppressed by forming N type dopant diffusion barriers in the stacked silicon layers of the gate structure; and (3) the side effects of the heavy nitrogen ion implantation could be avoided.
REFERENCES:
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 5670397 (1997-09-01), Chang et al.
patent: 5710454 (1998-01-01), Wu
patent: 5767004 (1998-06-01), Balasubramanian et al.
patent: 5817547 (1998-10-01), Eom
patent: 5891794 (1999-04-01), Ibok
patent: 5972761 (1999-10-01), Wu
patent: 6043142 (2000-03-01), Nakajima et al.
Chaudhuri Olik
Coleman William David
Texas Instruments--Acer Incorporated
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