Method of removing oxynitride by forming an offset spacer

Details Method of removing oxynitride by forming an offset spacer Method of removing oxynitride by forming an offset spacer

1999-09-08

2001-02-13

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S595000, C438S952000

Reexamination Certificate

active

06187644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for improving SiON residue oxide problem by forming a sidewall offset spacer.
2. Description of the Prior Art
As the semiconductor device, such as metal oxide semiconductor (MOS), becomes highly integrated, the area occupied by the device shrinks, as well as the design rule.
As the MOS devices are scaled down to about 0.18 micrometer or below, a SiON layer is usually deposited on the surface of a polygate, serving as an anti-reflective coating and critical dimension (CD) control. Unfortunately, the use of this SiON layer has some side effects on the formation of the MOS devices. For example, the surface of the SiON layer is apt to be oxidized. This surface oxide disadvantageously retards the following SiON removing by H
3
PO
4
etching. Further, the H
3
PO
4
etchant will attack the polygate, resulting in polysilicon peeling.
For the foregoing reasons, there is a need for a method of improving SiON residue oxide problem and the polysilicon peeling issue while forming a semiconductor device.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a semiconductor device that substantially improves the SiON residue problem by simultaneously removing SiON surface oxide during the formation of the offset spacer.
Another object of the present invention is to eliminate the implanted polysilicon peeling problem by use of the offset spacer.
A further object of the present invention is to reduce the capacitance between the gate and the drain (C
gd
), thereby enhancing device performance.
In one embodiment, the present invention includes firstly providing a semiconductor substrate having at least one shallow trench isolation (STI) region formed therein. Next, a gate oxide layer and a polysilicon layer are formed over substrate. After implanting the polysilicon layer, an oxynitride layer is deposited on the polysilicon layer, wherein the oxynitride layer serves as an anti-reflective coating. A photoresist layer is then formed on the oxynitride layer to define a gate region. After etching the oxynitride layer and the polysilicon layer, a gate region is thus formed. A dielectric layer is deposited over the gate region, followed by anisotropically etching back the dielectric layer to form an offset spacer on sidewall of the gate region while simultaneously removing surface oxide of the oxynitride layer. Finally, the oxynitride layer is removed using a wet etch.


REFERENCES:
patent: 5891784 (1999-04-01), Cheung et al.
patent: 5902125 (1999-05-01), Wu
patent: 6004853 (1999-12-01), Yang et al.
patent: 6063704 (2000-05-01), Demirlioglu

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