Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-03
2001-05-29
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S223000, C438S221000
Reexamination Certificate
active
06238959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more particularly to a method for forming a lateral diffused metal-oxide-semiconductor (LDMOS) transistor.
2. Description of the Prior Art
Power semiconductor devices are currently being used in many applications. Such power devices include high-voltage integrated circuits which typically include one or more high-voltage transistors, often on the same chip as low-voltage circuitry. A commonly used high-voltage component for these circuits is the lateral double diffused MOS transistor (LDMOS). LDMOS structures used in the high-voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. In general, these existing LDMOS structures are fabricated in a thick epitaxial layer of opposite conductivity type to the substrate.
High-power applications have called for the use of such lateral double diffused MOS transistors primarily because they possess lower “on” resistance, faster switching speed, and lower gate drive power dissipation than their bi-polar counterparts. These devices have heretofore also been strongly associated with bi-polar based process flows when integrated into a Bi-CMOS environment.
On the development of ultra-large-scale-integrated (ULSI), the layout rule will shrink and the application of product is going to develop on a multi-chip of integrated function. The prior LDMOS transistor is implemented by LOCOS process. Referring to
FIG. 1
, an N-type well
112
and a P-type well
110
with lighter concentration are formed in a P-type substrate
100
, and a field oxide (fox) region
120
is formed between gate
140
and source/drain
114
A. However, such process could not meet the requirement of the layout rule in ULSI.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming LDMOS transistor that substantially can decrease the width of the LDMOS transistor.
It is another object of this invention to provide an integrated trench oxide process in the formation of an LDMOS transistor.
In one embodiment, a method for forming the LDMOS transistor is disclosed. The method includes providing a substrate having a first conductivity type and then forming a first high-voltage region with second conductivity type opposite to the first conductivity type. Then, a second high-voltage region with the first conductivity type is formed adjacent to and in contact with the first high-voltage region, and at least one trench isolation region is formed in the first high-voltage region. Next, a first low-voltage region is formed in the first high-voltage region, such that the trench isolation region is included in the first low-voltage region. A second low-voltage region is formed in the second high-voltage region. A gate structure is formed adjacent to and partially overlapping between the trench isolation region and the second low-voltage region. A first source/drain region is formed in the first low-voltage region and a second source/drain region is formed in the second low-voltage region adjacent opposite sides of the gate structure in the top surface of the substrate.
REFERENCES:
patent: 5252848 (1993-10-01), Adler
patent: 5825065 (1998-10-01), Corsi et al.
patent: 6144069 (2000-11-01), Tung
Nguyen Tuan H.
United Microelectronics Corp.
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