Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-02
2001-12-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06329242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates in general to semiconductor memory devices, and more particularly to a structure of a dynamic random access memory (DRAM) cell substantially composed of a transfer transistor and a charge storage capacitor.
2. Description of the Related Art:
FIG. 1
is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell is substantially composed of a transfer transistor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain thereof is connected to a storage electrode
6
of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposing electrode
8
of the capacitor C is connected to a constant power source. A dielectric film
7
is provided between the storage electrode
6
and the opposing electrode
8
.
In the DRAM manufacturing process, a two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, so that the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration. For a high integration DRAM such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, called a stacked-type or a trench-type capacitor, has been introduced.
With the stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory in a similar volume. However, to realize a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type, turns out to be insufficient.
One solution for improving the capacitance of a capacitor is to use the so-called fin-type stacked capacitor, which is proposed in Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs”, International Electron Devices meeting, pp. 592-595, December 1988. The fin-type stacked capacitor includes electrodes and dielectric films which extend in a fin shape in a plurality of stacked layers. DRAMs having the fin-type stacked capacitor are also disclosed in U.S. Pat. No. 5,071,783 (Taguchi et al.); U.S. Pat. No. 5,126,810 (Gotou), U.S. Pat. No. 5,196,365 (Gotou); and U.S. Pat. No. 5,206,787 (Fujioka).
Another solution for improving the capacitance of a capacitor is to use the so-called cylindrical-type stacked capacitor, which is proposed in Wakamiya et al., “Novel Stacked Capacitor Cell for 64-Mb DRAM”, 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. A DRAM having the cylindrical-type stacked capacitor also is disclosed in the U.S. Pat. No. 5,077,688 (Kumanoya et al.).
With the trend toward increased integration density, the size of the DRAM cell in a plane (the area it occupies in a plane) must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacity (capacitance). Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of &agr;-rays is increased. Therefore, there is still a need in this art to design a new structure of a storage capacitor which can achieve the same capacitance, while occupying a smaller area in a plane, and a suitable method of fabricating the structure.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for fabricating a semiconductor memory device which is structured with a tree-type capacitor that allows an increased area for charge storage.
In accordance with the foregoing and other objects of the invention, a new and improved method for fabricating a semiconductor memory device are provided.
The invention provides a method for fabricating a semiconductor memory device. The semiconductor memory device includes a substrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions. According to the method, a first insulating, layer is first formed over the substrate, such that it covers the transfer transistor. An insulating pillar is then formed over the first insulating layer, the insulating pillar defining recess areas on either side thereof. A first film of insulating material and a second film of conductive material are next alternately formed over the first insulating layer in a recess area and over the insulating pillar. A selected part of the second film that lies above the insulating pillar is then removed and a first conductive layer is formed which penetrates at least through the second film, the first film, and the first insulating layer so as to be electrically coupled to one of the source/drain regions The first conductive layer and the second film in combination thus form a storage electrode of the charge storage capacitor. The insulating pillar and the first film are then removed. A dielectric layer is formed over exposed surfaces of the first conductive layer and the second film, and a second conductive layer is formed over the dielectric layer. The second conductive layer thus functions as an opposing electrode of the charge storage capacitor.
A semiconductor memory device according to the invention is therefore formed having a tree-type capacitor of increased area for reliable storage thereon of electrical charges representative of data. By varying the number of conducting layers formed, interleaved with insulating layers, during fabrication, the total surface area of the capacitor electrodes can be controlled. The size, shape, and placement of the insulating pillar and the size, shape, and construction of the second conductive layer may also be varied to change the shape of the tree-type capacitor in order to satisfy particular design needs.
REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5089869 (1992-02-01), Matsuo et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5126810 (1992-06-01), Gotou
patent: 5142639 (1992-08-01), Kohyama et al.
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5158905 (1992-10-01), Ahn
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5172201 (1992-12-01), Suizu
patent: 5196365 (1993-03-01), Gotou
patent: 5206787 (1993-04-01), Fujioka
patent: 5266512 (1993-11-01), Kirsch
patent: 5274258 (1993-12-01), Ahn
patent: 5338955 (1994-08-01), Tamura et al.
patent: 5354704 (1994-10-01), Yang et al.
patent: 5371701 (1994-12-01), Lee et al.
patent: 5389568 (1995-02-01), Yun
patent: 5399518 (1995-03-01), Sim et al.
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5443993 (1995-08-01), Park et al.
patent: 5453633 (1995-09-01), Yun
patent: 5460996 (1995-10-01), Ryou
patent: 5478768 (1995-12-01), Iwasa
patent: 5478770 (1995-12-01), Kim
patent: 5482886 (1996-01-01), Park et al.
patent: 5508222 (1996-04-01), Sakao
patent: 5521419 (1996-05-01), Wakamiya et al.
patent: 5523542 (1996-06-01), Chen et al.
patent: 5543346 (1996-08-01), Keum et al.
patent: 5550080 (1996-08-01), Kim
patent: 5561309 (1996-10-01), Cho et al.
patent: 5561310 (1996-10-01), Woo et al.
patent: 5572053 (1996-11-01), Ema
patent: 5595931 (1997-01-01), Kim
patent: 0 516 031 A1 (1992-12-01), None
patent: 2 252 447 A (1992-08-01), None
patent: 4-26156 (1992-01-01), None
patent: 5-27145 A (1993-01-01), None
patent: 5-251657 (1993-09-01), None
“Mini-Trenches in Polysilicon For Dram Storage Capacitance Enhancement”, IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991.
Wakamiya et al., “Novel Stacked Capacitor Cell
Rabin & Berdo P.C.
Tsai Jey
United Microelectronics Corp.
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