Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-05-19
2001-02-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S951000
Reexamination Certificate
active
06194272
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits (“ICs”), and more particularly to a split-gate flash cell, as may be incorporated in a electronically programmable read only memory (EPROM).
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve the improvements in complexity and circuit density, i.e., the number of devices capable of being packed onto a given chip area, the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Currently, devices are being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility.
Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to align one layer of the device to a preceding layer of the device.
Several photolithographic steps are commonly used in the fabrication sequence of an integrated circuit. Photolithography is a process that uses a “mask” to expose selected portions of the surface of the wafer or substrate to light, which is shined through the clear portions of the mask. The surface of the wafer is typically coated with a photoresist, and after exposure of selected portions of the photoresist to the light, the photoresist is developed, so that a patterned layer of photoresist remains on the surface of the wafer. Then, any one of several processes, such as an etch process or an implantation process, may be performed to create a selected pattern on or in the substrate, after which process the photoresist is typically stripped. In some conventional fabrication processes each layer of photoresist or patterned material is aligned to the layer or layers below it.
FIG. 1
is a simplified cross section of a split-gate flash cell that illustrates how the need to align one layer to another can limit the smallest size of the device. A first gate 10 patterned from a first layer of polysilicon is formed on the field oxide 12 of the wafer 20. A dielectric layer 14 is formed over the first gate and then, a second layer of polysilicon is formed over the wafer and patterned to form a second gate 16. The second gate has a channel region 18 and an overlap region 22. The overlap region 22 leaves an exposed portion 24 of the first gate 10 that is not covered by the second gate 16.
It is important to accurately align the pattern of the second polysilicon layer to the pattern of the first polysilicon layer. For example, if the exposed portion 24 of the first gate 10 is too small, the second gate 16 may completely cover the first gate 10 and cell program efficiency will degrade in some circumstances. For example, if the floating gate is programmed with channel hot electrons, the hot carrier energy will degrade because V
DS
will be divided between the first and second polysilicon gaps. If the overlap region 22 is too small, the first gate 10 and second gate 16 may not properly electrically couple, and if the channel region 18 is too small, the transistor may leak, or there may be no operating channel region at all. Therefore, when aligning the mask that will define the features in the second polysilicon layer, it is important that the edge 26 of the second gate 16 is accurately placed in relation to the first gate 10.
If the sizes of the first gate and second gate are not large enough to accommodate the variation associated with the alignment process, some yield loss will occur due to misalignment. Thus, the dimensions of the first and second gate are typically large enough to be compatible with conventional photomask alignment processes and to provide acceptable yields. This may result in device structures that are larger than they need to be for proper circuit operation.
Therefore, it is desirable to provide a multi-gate cell structure that does not require multi-layer alignment of the gates.
SUMMARY OF THE INVENTION
The present invention provides a dual-gate device structure with a small cell size. Such a dual-gate device structure may be used in a split-gate flash cell, for example.
In an exemplary embodiment, a second gate structure is formed by depositing polysilicon over and adjacent to a first gate structure. The second gate structure is separated from the first gate structure by a layer of dielectric material. The second gate is self-aligned to the first gate, so that no photolithographic alignment tolerance is required between these two structures. The first gate and second gate are formed on a substrate having a first conductivity type. Drain and source regions of a second conductivity type are formed in the substrate proximate to the first gate and second gate, separated by a channel region. A dielectric layer separates the first gate from the substrate and a second dielectric layer separates the second gate from the substrate, and a channel region may be formed in the substrate below the gates. In a further embodiment, a pocket region with a higher doping concentration of the first doping type is formed under the second gate to inhibit a conductive channel from forming when not desired.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.
REFERENCES:
patent: 4754320 (1988-06-01), Mizutani
patent: 4997781 (1991-03-01), Tigelaar
patent: 5063172 (1991-11-01), Manley
patent: 5143860 (1992-09-01), Mitchell et al.
patent: 5379255 (1995-01-01), Shah
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5476801 (1995-12-01), Keshtbod
patent: 5587332 (1996-12-01), Chang et al.
patent: 5614747 (1997-03-01), Ahn et al.
patent: 5683923 (1997-11-01), Shimizu et al.
patent: 5702965 (1997-12-01), Kim
patent: 5707897 (1998-01-01), Lee et al.
patent: 5923978 (1999-07-01), Hisamune et al.
Booth Richard
Mosel Vitelic Inc.
Townsend and Townsend / and Crew LLP
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